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1. 发明授权

US09589621B2 Resistance change memory 有权
标题翻译：电阻变化记忆
公开(公告)号：US09589621B2
公开(公告)日：2017-03-07
申请号：US14988144
申请日：2016-01-05
申请人： Katsuyuki Fujita
发明人： Katsuyuki Fujita
IPC分类号： G11C11/16 , G11C11/14 , G11C11/02 , G11C7/04 , G11C29/44 , G11C7/10 , G06F11/00 , G11C11/56 , G11C7/08 , G11C16/26 , G11C13/00 , G11C29/04
CPC分类号： G11C11/1675 , G06F11/00 , G06F11/3037 , G06F11/3058 , G11C7/04 , G11C7/08 , G11C7/1006 , G11C11/16 , G11C11/1673 , G11C11/1693 , G11C11/5607 , G11C13/004 , G11C13/0069 , G11C16/26 , G11C29/44 , G11C2013/0052 , G11C2013/0092 , G11C2029/0411
摘要： A resistance change memory includes a memory cell array comprising memory cells including magnetic tunnel junction (MTJ) elements; a write and read circuit which performs a write operation and a read operation for the memory cells; a temperature sensor which outputs temperature information corresponding to a temperature of the memory cell array; and a memory controller which controls the write operation and the read operation by the write and read circuit in response to the temperature information, such that a first time period from a write command input to a pre-charge command input is variable according to the temperature information, while a second time period from an active command input to the pre-charge command input is fixed constant regardless of the temperature information.
摘要翻译：电阻变化存储器包括存储单元阵列，其包括包括磁性隧道结（MTJ）元件的存储单元; 写入和读取电路，用于对存储器单元执行写入操作和读取操作; 温度传感器，其输出与存储单元阵列的温度对应的温度信息; 以及存储器控制器，其响应于温度信息控制写入和读取电路的写入操作和读取操作，使得从写入命令输入到预充电命令输入的第一时间段根据温度而变化信息，而从活动命令输入到预充电命令输入的第二时间段不管温度信息如何都是固定的。

2. 发明授权

US09502140B2 Semiconductor memory device 有权
公开(公告)号：US09502140B2
公开(公告)日：2016-11-22
申请号：US14799066
申请日：2015-07-14
申请人： Katsuyuki Fujita
发明人： Katsuyuki Fujita
IPC分类号： G11C7/00 , G11C29/00 , G11C11/16 , G11C29/04
CPC分类号： G11C29/76 , G11C11/161 , G11C11/1653 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C29/04 , G11C29/787
摘要： According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address.

3. 发明申请

US20150318061A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20150318061A1
公开(公告)日：2015-11-05
申请号：US14799066
申请日：2015-07-14
申请人： Katsuyuki Fujita
发明人： Katsuyuki Fujita
IPC分类号： G11C29/00 , G11C29/04 , G11C11/16
CPC分类号： G11C29/76 , G11C11/161 , G11C11/1653 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C29/04 , G11C29/787
摘要： According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address.
摘要翻译：根据一个实施例，半导体存储器件包括连接到存储单元阵列的第一字线，连接到冗余区的第二字线，配置为基于行地址从第一字线执行选择的第一行解码器，判断电路，被配置为基于包括在行地址中的冗余地址来确定是否需要具有冗余区域的替换操作;以及第二行解码器，被配置为执行从第二字线的选择。行地址包括在分时方法中按顺序输入的第一行地址和第二行地址。第一行地址包括所有冗余地址。

4. 发明申请

US20150109855A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20150109855A1
公开(公告)日：2015-04-23
申请号：US14581507
申请日：2014-12-23
申请人： Katsuyuki FUJITA
发明人： Katsuyuki FUJITA
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1653 , G11C11/1675 , G11C11/1693
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer configured to hold data input to an input/output circuit and to hold data read from the memory cell array, and a controller configured to receive a first command and an address from the outside and to read data, in response to the first command, from a memory cell group coupled to a selected word line designated by the address to the buffer. The controller receives a second command which is input after the first command and indicates a last command of a group of commands including write commands and/or read commands, and starts a write operation from the buffer to the memory cell array in response to the second command.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，被配置为保持输入到输入/输出电路的数据并保持从存储单元阵列读取的数据的缓冲器以及被配置为接收第一命令和来自外部的地址，并且响应于第一命令从耦合到由该地址指定的所选字线的存储器单元组读取数据到缓冲器。控制器接收在第一命令之后输入的第二命令，并且指示包括写入命令和/或读取命令的一组命令的最后命令，并响应于第二命令从缓冲器开始到存储器单元阵列的写入操作命令。

5. 发明授权

US08498144B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US08498144B2
公开(公告)日：2013-07-30
申请号：US13191678
申请日：2011-07-27
申请人： Masahiro Takahashi , Katsuyuki Fujita , Yoshihiro Ueda , Katsuhiko Hoya
发明人： Masahiro Takahashi , Katsuyuki Fujita , Yoshihiro Ueda , Katsuhiko Hoya
IPC分类号： G11C11/00 , G11C11/15
CPC分类号： G11C8/10 , G11C8/08 , G11C11/1675 , G11C11/1693
摘要： A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a first resistance change element which is connected in series to the first selection transistor between the first bit line and the second bit line, and of which a resistance value changes according to a flowing current. The semiconductor storage device includes a second selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a second resistance change element which is connected in series to the second selection transistor between the second bit line and the third bit line, and of which a resistance value changes according to a flowing current.
摘要翻译：半导体存储装置包括第一至第四开关电路。半导体存储装置包括用于控制字线电压的行译码器。半导体存储装置包括控制端子连接到字线的第一选择晶体管。半导体存储装置包括与第一位线和第二位线之间的第一选择晶体管串联连接的第一电阻变化元件，其电阻值根据流动电流而变化。半导体存储装置包括控制端子连接到字线的第二选择晶体管。半导体存储装置包括与第二位线和第三位线之间的第二选择晶体管串联连接的第二电阻变化元件，其电阻值根据流动电流而变化。

6. 发明授权

US08233310B2 Resistance-change memory 有权
标题翻译：电阻变化记忆
公开(公告)号：US08233310B2
公开(公告)日：2012-07-31
申请号：US12847892
申请日：2010-07-30
申请人： Katsuyuki Fujita , Shinichiro Shiratake
发明人： Katsuyuki Fujita , Shinichiro Shiratake
IPC分类号： G11C11/00 , G11C11/14 , G11C11/15
CPC分类号： G11C11/1675 , G11C11/161 , G11C11/1659 , G11C11/1673
摘要： According to one embodiment, a resistance-change memory includes bit lines running in a first direction, word lines running in a second direction, and a memory cell array includes memory cells each includes a selection transistor and a variable resistance element. In a layout of first to fourth variable resistance elements arranged in order in the first direction, the first variable resistance element and the second variable resistance element sandwich one word line therebetween, the third variable resistance element and the fourth variable resistance element sandwich one word line therebetween, a first pair includes the first and second variable resistance elements and a second pair includes the third and fourth variable resistance elements sandwich two word lines therebetween, and a column is constructed by repeating the layout in the first direction.
摘要翻译：根据一个实施例，电阻变化存储器包括沿第一方向运行的位线，在第二方向上运行的字线，以及包括选择晶体管和可变电阻元件的存储单元阵列。在第一至第四可变电阻元件的布置中，第一可变电阻元件和第二可变电阻元件之间夹着一条字线，第三可变电阻元件和第四可变电阻元件夹着一条字线其间，第一对包括第一和第二可变电阻元件，第二对包括第三和第四可变电阻元件，夹着两条字线，并且通过在第一方向重复布局来构造列。

7. 发明申请

US20120063215A1 SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：半导体存储设备
公开(公告)号：US20120063215A1
公开(公告)日：2012-03-15
申请号：US13191678
申请日：2011-07-27
申请人： Masahiro TAKAHASHI , Katsuyuki Fujita , Yoshihiro Ueda , Katsuhiko Hoya
发明人： Masahiro TAKAHASHI , Katsuyuki Fujita , Yoshihiro Ueda , Katsuhiko Hoya
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C8/08 , G11C11/1675 , G11C11/1693
摘要： A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a first resistance change element which is connected in series to the first selection transistor between the first bit line and the second bit line, and of which a resistance value changes according to a flowing current. The semiconductor storage device includes a second selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a second resistance change element which is connected in series to the second selection transistor between the second bit line and the third bit line, and of which a resistance value changes according to a flowing current.
摘要翻译：半导体存储装置包括第一至第四开关电路。半导体存储装置包括用于控制字线电压的行译码器。半导体存储装置包括控制端子连接到字线的第一选择晶体管。半导体存储装置包括与第一位线和第二位线之间的第一选择晶体管串联连接的第一电阻变化元件，其电阻值根据流动电流而变化。半导体存储装置包括控制端子连接到字线的第二选择晶体管。半导体存储装置包括与第二位线和第三位线之间的第二选择晶体管串联连接的第二电阻变化元件，其电阻值根据流动电流而变化。

8. 发明申请

US20090147226A1 Inner Surface Exposure Apparatus and Inner Surface Exposure Method Technical Field 审中-公开
标题翻译：内表面曝光装置及内表面曝光方法技术领域
公开(公告)号：US20090147226A1
公开(公告)日：2009-06-11
申请号：US12087651
申请日：2006-12-25
申请人： Toshiyuki Horiuchi , Katsuyuki Fujita , Takashi Yasuda
发明人： Toshiyuki Horiuchi , Katsuyuki Fujita , Takashi Yasuda
IPC分类号： G03B27/42
CPC分类号： G03F7/24 , G03F7/703
摘要： An apparatus and a method for exposing a photosensitive material deposited on the inner surface of a tube such as a circular or polygonal tube to light to form a predetermined exposed pattern are provided. The apparatus includes: a guide rod that is inserted into the inner space of an exposure object and emits an exposure light beam toward the inner side of the exposure object; and a stage for changing the relative positions of the exposure object and the guide rod and/or the relative angle between the exposure object and the guide rod. After the irradiation spot of the exposure light beam is brought into focus and/or is adjusted to an exposure starting point, the exposure light beam is projected onto a predetermined position on the exposure object to form a predetermined exposed pattern of a photosensitive material deposited on the inner surface of the exposure object.
摘要翻译：提供了一种用于将沉积在诸如圆形或多边形管的管的内表面上的感光材料曝光以形成预定的暴露图案的装置和方法。该装置包括：导杆，其被插入到曝光对象的内部空间中，并且朝向曝光对象的内侧发射曝光光束; 以及用于改变曝光对象和导杆的相对位置和/或曝光对象与导杆之间的相对角度的台。在曝光光束的照射点被聚焦和/或被调整到曝光开始点之后，曝光光束被投射到曝光对象上的预定位置上，以形成沉积在其上的感光材料的预定曝光图案曝光对象的内表面。

9. 发明授权

US07494537B2 Thermochromic coloring color-memory composition and thermochromic coloring color-memory microcapsule pigment containing the same 有权
标题翻译：热变色着色色记忆组合物和含有其的热致色着色色记忆微胶囊颜料
公开(公告)号：US07494537B2
公开(公告)日：2009-02-24
申请号：US11273080
申请日：2005-11-15
申请人： Yoshiaki Ono , Katsuyuki Fujita
发明人： Yoshiaki Ono , Katsuyuki Fujita
IPC分类号： C09D11/00
CPC分类号： B41M5/305 , B41M5/337 , C09D11/17
摘要： A thermochromic coloring color-memory composition comprising a homogeneous solubilized mixture of (A) an electron donative coloring organic compound, (B) an electron accepting compound and (C) a compound represented by the specific formula as a reaction medium which controls color reactions of the components (A) and (B).
摘要翻译：一种热致变色着色记录组合物，其包含（A）给电子着色有机化合物，（B）电子接受性化合物和（C）作为反应介质的化合物作为反应介质的均匀溶解混合物，其控制着色反应组分（A）和（B）。

10. 发明授权

US07480198B2 Semiconductor memory device and driving method of semiconductor memory device 失效
标题翻译：半导体存储器件及半导体存储器件的驱动方法
公开(公告)号：US07480198B2
公开(公告)日：2009-01-20
申请号：US11680999
申请日：2007-03-01
申请人： Katsuyuki Fujita
发明人： Katsuyuki Fujita
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C7/12 , G11C7/18 , G11C11/404 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005 , G11C2207/2281 , G11C2211/4016
摘要： This disclosure concerns a semiconductor memory device comprising memory cells; word lines connected to gates of the memory cells; bit lines connected to drains or sources of the memory cells and transmitting data of the memory cells; sense nodes connected to the bit lines and transmitting data of the memory cells; transfer gates connected to between the bit lines and the sense nodes; and latch circuits latching data to the sense nodes, wherein in a data read operation, a selection word line is in an inactive state during a latch period which is from immediately before the latch circuits start a data latch operation until when the transfer gate disconnects the bit lines from the sense nodes after the latch operation, the selection word line being one of the word lines and being connected to selection memory cells from which data is to be read to the sense nodes.
摘要翻译：本公开涉及包括存储器单元的半导体存储器件; 连接到存储器单元的门的字线; 连接到存储器单元的漏极或源极的位线，并传送存储器单元的数据; 连接到位线的感测节点和发送存储器单元的数据; 连接到位线和感测节点之间的传输门; 并且锁存电路将数据锁存到感测节点，其中在数据读取操作中，在从锁存电路开始数据锁存操作之前的锁存时段期间，选择字线处于非活动状态，直到传输门断开在锁存操作之后，来自感测节点的位线，选择字线是字线之一，并且连接到选择存储器单元，数据将从其读取到感测节点。

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