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1. 发明授权

US08369129B2 Semiconductor memory device with variable resistance element 有权
标题翻译：具有可变电阻元件的半导体存储器件
公开(公告)号：US08369129B2
公开(公告)日：2013-02-05
申请号：US12818028
申请日：2010-06-17
申请人： Katsuyuki Fujita , Kenji Tsuchida
发明人： Katsuyuki Fujita , Kenji Tsuchida
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C2013/0054
摘要： According to one embodiment, a semiconductor memory device includes a variable resistance element configured to store data “0” and data “1” in accordance with a change in resistance value, a current generator configured to generate a reference current for determining data of the variable resistance element, and having an admittance middle between an admittance of a variable resistance element storing data “0” and an admittance of a variable resistance element storing data “1”, and a sense amplifier includes a first input terminal connected to the variable resistance element and a second input terminal connected to the current generator, and configured to compare currents of the first input terminal and the second input terminal.
摘要翻译：根据一个实施例，半导体存储器件包括可变电阻元件，其被配置为根据电阻值的变化来存储数据0和数据1;电流发生器，被配置为产生用于确定可变电阻元件的数据的参考电流;以及在存储数据0的可变电阻元件的导纳与存储数据1的可变电阻元件的导纳之间的导纳中心处的导纳和感测放大器包括连接到可变电阻元件的第一输入端子和连接到可变电阻元件的第二输入端子电流发生器，并且被配置为比较第一输入端子和第二输入端子的电流。

2. 发明申请

US20100321980A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100321980A1
公开(公告)日：2010-12-23
申请号：US12818028
申请日：2010-06-17
申请人： Katsuyuki Fujita , Kenji Tsuchida
发明人： Katsuyuki Fujita , Kenji Tsuchida
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C2013/0054
摘要： According to one embodiment, a semiconductor memory device includes a variable resistance element configured to store data “0” and data “1” in accordance with a change in resistance value, a current generator configured to generate a reference current for determining data of the variable resistance element, and having an admittance middle between an admittance of a variable resistance element storing data “0” and an admittance of a variable resistance element storing data “1”, and a sense amplifier includes a first input terminal connected to the variable resistance element and a second input terminal connected to the current generator, and configured to compare currents of the first input terminal and the second input terminal.
摘要翻译：根据一个实施例，半导体存储器件包括可变电阻元件，其被配置为根据电阻值的变化存储数据“0”和数据“1”;电流发生器，被配置为产生用于确定变量数据的参考电流电阻元件，并且在存储数据“0”的可变电阻元件的导纳与存储数据“1”的可变电阻元件的导纳之间的导纳中间具有导纳，以及读出放大器包括连接到可变电阻元件的第一输入端子以及连接到所述电流发生器的第二输入端子，并且被配置为比较所述第一输入端子和所述第二输入端子的电流。

3. 发明授权

US09257167B2 Resistance change memory 有权
标题翻译：电阻变化记忆
公开(公告)号：US09257167B2
公开(公告)日：2016-02-09
申请号：US14482904
申请日：2014-09-10
申请人： Katsuyuki Fujita
发明人： Katsuyuki Fujita
IPC分类号： G11C11/16 , G11C11/14 , G11C7/04 , G11C11/02 , G11C29/44 , G11C11/56 , G11C7/08 , G11C16/26 , G11C13/00 , G11C29/04
CPC分类号： G11C11/1675 , G06F11/00 , G06F11/3037 , G06F11/3058 , G11C7/04 , G11C7/08 , G11C7/1006 , G11C11/16 , G11C11/1673 , G11C11/1693 , G11C11/5607 , G11C13/004 , G11C13/0069 , G11C16/26 , G11C29/44 , G11C2013/0052 , G11C2013/0092 , G11C2029/0411
摘要： According to one embodiment, a resistance change memory comprises a memory cell array, a write and read circuit, a temperature sensor, and a memory controller. The memory cell array comprises memory cells including magnetic tunnel junction (MTJ) elements. The write and read circuit performs a write operation and a read operation for the memory cells. The temperature sensor outputs temperature information corresponding to a temperature of the memory cell array. The memory controller controls the write operation and the read operation by the write and read circuit in accordance with the temperature information.
摘要翻译：根据一个实施例，电阻变化存储器包括存储单元阵列，写入和读取电路，温度传感器和存储器控制器。存储单元阵列包括包括磁性隧道结（MTJ）元件的存储单元。写入和读取电路对存储器单元执行写入操作和读取操作。温度传感器输出与存储单元阵列的温度对应的温度信息。存储器控制器根据温度信息控制写入和读取电路的写入操作和读取操作。

4. 发明授权

US08947918B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08947918B2
公开(公告)日：2015-02-03
申请号：US14014231
申请日：2013-08-29
申请人： Katsuyuki Fujita
发明人： Katsuyuki Fujita
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1653 , G11C11/1675 , G11C11/1693
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer configured to hold data input to an input/output circuit and to hold data read from the memory cell array, and a controller configured to receive a first command and an address from the outside and to read data, in response to the first command, from a memory cell group coupled to a selected word line designated by the address to the buffer. The controller receives a second command which is input after the first command and indicates a last command of a group of commands including write commands and/or read commands, and starts a write operation from the buffer to the memory cell array in response to the second command.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，被配置为保持输入到输入/输出电路的数据并保持从存储单元阵列读取的数据的缓冲器以及被配置为接收第一命令和来自外部的地址，并且响应于第一命令从耦合到由该地址指定的所选字线的存储器单元组读取数据到缓冲器。控制器接收在第一命令之后输入的第二命令，并且指示包括写入命令和/或读取命令的一组命令的最后命令，并响应于第二命令从缓冲器开始到存储器单元阵列的写入操作命令。

5. 发明授权

US08282299B2 Friction body, writing instrument and writing instrument set 有权
标题翻译：摩擦体，书写工具和书写工具组
公开(公告)号：US08282299B2
公开(公告)日：2012-10-09
申请号：US11946071
申请日：2007-11-28
申请人： Yoshihiro Ito , Shouichi Ohkawa , Katsuyuki Fujita
发明人： Yoshihiro Ito , Shouichi Ohkawa , Katsuyuki Fujita
IPC分类号： B43K29/00
CPC分类号： B43K29/02 , B43K1/086 , B43K7/02 , B43K7/10 , B43K8/04 , B43K8/06 , B43K23/12 , B43K23/126 , B43L19/0025 , B43L19/0068 , C09D11/16 , C09D11/18 , C09D11/50
摘要： A friction body that produces frictional heat allowing development, disappearance or change of color of handwriting formed with a writing instrument for producing thermochromic handwriting, with the friction body having a friction coefficient of 0.2 to 1.0 when rubbed against paper surface, and a writing instrument for use in forming thermochromic handwriting which is equipped with the friction body and a writing instrument set including the friction body and a writing instrument for use in forming thermochromic handwriting.
摘要翻译：产生摩擦热的摩擦体，其允许由用于产生热变色手写的书写工具形成的笔迹的显影，消失或变化，摩擦体摩擦纸面摩擦系数为0.2至1.0;以及书写工具用于形成配备有摩擦体的热变色手写体和包括摩擦体的书写工具组和用于形成热变色手写的书写工具。

6. 发明授权

US07675793B2 Semiconductor memory device and driving method for the device 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07675793B2
公开(公告)日：2010-03-09
申请号：US12033258
申请日：2008-02-19
申请人： Katsuyuki Fujita
发明人： Katsuyuki Fujita
IPC分类号： G11C7/00
CPC分类号： G11C11/404 , G11C11/4076 , G11C2211/4016
摘要： This disclosure concerns a semiconductor memory device comprising: memory cells including floating bodies storing data; word lines connected to gates of the memory cells; a bit line pair connected to the memory cells and transmitting data stored in the memory cells; a sense node pair connected to the bit line pair and transmitting data stored in the memory cells; transfer gates connected between the bit line pair and the sense node pair; latch circuits latching a high-level potential in one sense node of the sense node pair, and latching a first low-level potential in the other sense node of the sense node pair; and a level shifter applying a second low-level potential lower than the first low-level potential to one bit line of the bit line pair according to the electric potentials latched in the sense node pair at the time of writing data or writing back data.
摘要翻译：本公开涉及一种半导体存储器件，包括：存储单元，其包括存储数据的浮动体; 连接到存储器单元的门的字线; 连接到存储器单元并发送存储在存储单元中的数据的位线对; 感测节点对，连接到所述位线对并发送存储在所述存储单元中的数据; 连接在位线对和感测节点对之间的传输门; 锁存电路锁存感测节点对的一个感测节点中的高电平电位，并且锁存感测节点对的另一个感测节点中的第一低电平电位; 以及电平移位器，根据在写入数据或写入数据时锁存在感测节点对中的电位，将比第一低电平电位低的第二低电平电位施加到位线对的一个位线。

7. 发明授权

US07539069B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07539069B2
公开(公告)日：2009-05-26
申请号：US11748187
申请日：2007-05-14
申请人： Katsuyuki Fujita
发明人： Katsuyuki Fujita
IPC分类号： G11C7/00
CPC分类号： G11C8/10 , G11C7/065 , G11C7/12 , G11C11/404 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2211/4016
摘要： This disclosure concerns a memory comprising a memory cell; a first and a second sense nodes transmitting the data on the first and the second bit lines which transmits data with reversed polarities from each other; a first transfer gate provided between the first bit line and the first sense node; a second transfer gate provided between the second bit line and the second sense node; a latch circuit provided between the first and the second sense nodes; a write signal line activated when the data is written or restore to the cell; and a gate circuit connecting the write signal line to the first bit line and the first sense node to the second bit line, or connecting the write signal line to the second bit line and the second sense node to the first bit line, when the data is written or restore.
摘要翻译：本公开涉及包括存储器单元的存储器; 第一和第二感测节点，以相反极性传输数据的第一和第二位线发送数据; 设置在第一位线和第一感测节点之间的第一传送门; 提供在第二位线和第二感测节点之间的第二传输门; 设置在第一和第二感测节点之间的锁存电路; 当数据被写入或恢复到单元时，写入信号线被激活; 以及门电路，其将所述写信号线与所述第一位线和所述第一感测节点连接到所述第二位线，或者当所述数据与所述第一位线连接时，将所述写入信号线连接到所述第二位线和所述第二感测节点到所述第一位线是写或还原。

8. 发明授权

US07269084B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07269084B2
公开(公告)日：2007-09-11
申请号：US11056243
申请日：2005-02-14
申请人： Kosuke Hatsuda , Takashi Ohsawa , Katsuyuki Fujita
发明人： Kosuke Hatsuda , Takashi Ohsawa , Katsuyuki Fujita
IPC分类号： G11C7/02
CPC分类号： G11C7/14 , G11C11/404 , G11C11/4091 , G11C11/4099 , G11C2211/4016
摘要： The disclosure concerns a semiconductor memory device that includes memory cells that store data by accumulating or discharging an electric charge; memory cell arrays having a plurality of the memory cells disposed in a matrix; a plurality of word lines connected to the memory cells arrayed in rows of the memory cell arrays; a plurality of bit lines connected to the memory cells arrayed in columns of the memory cell arrays; a plurality of dummy cells arrayed in a row direction of the memory cell arrays and are connected to the bit lines; sense amplifiers detecting data within the memory cells by using an average value of electric characteristics of the dummy cells that store mutually different digital data as a reference signal; and a plurality of switching elements electrically connecting four or more of the bit lines in order to generate the reference signal.
摘要翻译：本公开涉及一种半导体存储器件，其包括通过累积或放电来存储数据的存储器单元; 具有设置在矩阵中的多个存储单元的存储单元阵列; 连接到排列在存储单元阵列中的存储单元的多个字线; 多个位线连接到存储单元阵列的列中排列的存储单元; 多个虚拟单元排列在存储单元阵列的行方向上并连接到位线; 读出放大器通过使用存储相互不同的数字数据的虚拟单元的电特性的平均值作为参考信号来检测存储单元内的数据; 以及电连接四个或更多个位线以便产生参考信号的多个开关元件。

9. 发明申请

US20060274590A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20060274590A1
公开(公告)日：2006-12-07
申请号：US11444487
申请日：2006-06-01
申请人： Katsuyuki Fujita , Kosuke Hatsuda , Takashi Ohsawa
发明人： Katsuyuki Fujita , Kosuke Hatsuda , Takashi Ohsawa
IPC分类号： G11C7/02
CPC分类号： G11C11/4091 , G11C7/065 , G11C11/406 , G11C2211/4016 , G11C2211/4065
摘要： A semiconductor memory device has first and second sense nodes which are provided corresponding to first and second bit lines, and a sense amplifier which is connected to the first and second sense nodes and senses data read out from a memory cell, wherein the sense amplifier includes an initial sense circuit which increases a potential difference between the first and second sense nodes in a first period after beginning sense operation, and a latch circuit which increases and holds the potential difference between the first and second sense nodes in a second period after the first period, wherein the initial sense circuit includes first and second transistors of first conductive type, third and fourth transistors of first conductive type, and fifth and sixth transistors of first conductive type, wherein the latch circuit includes seventh and eighth transistors of first conductive type, and ninth and tenth transistors of second conductive type.
摘要翻译：半导体存储器件具有对应于第一和第二位线提供的第一和第二感测节点，以及连接到第一和第二感测节点并感测从存储器单元读出的数据的读出放大器，其中读出放大器包括初始感测电路，其在开始感测操作之后的第一周期中增加第一和第二感测节点之间的电位差;以及锁存电路，其在第一和第二感测节点之后的第二周期中增加并保持第一和第二感测节点之间的电位差周期，其中所述初始检测电路包括第一导电类型的第一和第二晶体管，第一导电类型的第三和第四晶体管，以及第一导电类型的第五和第六晶体管，其中所述锁存电路包括第一和第八晶体管，以及第二导电类型的第九和第十晶体管。

10. 发明申请

US20060112851A1 Thermochromic coloring color-memory composition and thermochromic coloring color-memory microcapsule pigment containing the same 有权
公开(公告)号：US20060112851A1
公开(公告)日：2006-06-01
申请号：US11273080
申请日：2005-11-15
申请人： Yoshiaki Ono , Katsuyuki Fujita
发明人： Yoshiaki Ono , Katsuyuki Fujita
IPC分类号： C09D11/00
CPC分类号： B41M5/305 , B41M5/337 , C09D11/17
摘要： A thermochromic coloring color-memory composition comprising a homogeneous solubilized mixture of (A) an electron donative coloring organic compound, (B) an electron accepting compound and (C) a compound represented by the specific formula as a reaction medium which controls color reactions of the components (A) and (B).

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