专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07535061B2 Fin-field effect transistors (Fin-FETs) having protection layers 有权
标题翻译：具有保护层的鳍场效应晶体管（Fin-FET）
公开(公告)号：US07535061B2
公开(公告)日：2009-05-19
申请号：US11586225
申请日：2006-10-25
申请人： Deok-Hyung Lee , Si-Young Choi , Byeong-Chan Lee , In-Soo Jung , Jin-Hwa Heo
发明人： Deok-Hyung Lee , Si-Young Choi , Byeong-Chan Lee , In-Soo Jung , Jin-Hwa Heo
IPC分类号： H01L21/84
CPC分类号： H01L29/7851 , H01L29/66795
摘要： Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is provided on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is provided in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is provided on the first insulation layer and a second insulation layer is provided on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin.
摘要翻译：提供了场效应晶体管（Fin-FET）。翅片设置在集成电路基板上。翅片限定集成电路基板上的沟槽。第一绝缘层设置在沟槽中，使得第一绝缘层的表面在鳍片的暴露翅片侧壁的表面下方凹进。保护层设置在第一绝缘层上，第二绝缘层设置在沟槽中的保护层上，使得保护层位于第二绝缘层和鳍的侧壁之间。

2. 发明申请

US20090020805A1 NON-VOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20090020805A1
公开(公告)日：2009-01-22
申请号：US11950143
申请日：2007-12-04
申请人： Jin-Hwa Heo , Chul-Sung Kim , Bon-Young Koo , Ki-Hyun Hwang , Chang-Hyun Lee
发明人： Jin-Hwa Heo , Chul-Sung Kim , Bon-Young Koo , Ki-Hyun Hwang , Chang-Hyun Lee
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L21/28202 , H01L29/40117 , H01L29/4234 , H01L29/513 , H01L29/518
摘要： A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.
摘要翻译：非易失性存储器件包括电荷存储层和衬底之间的电介质层。可以减少电介质层的自由键，以减少/防止电荷通过游离键泄漏和/或被游离键捕获。结果，可以增强非挥发性存储器件的数据保持性能和/或耐久性。

3. 发明授权

US06756654B2 Structure of trench isolation and a method of forming the same 有权
标题翻译：沟槽隔离结构及其形成方法
公开(公告)号：US06756654B2
公开(公告)日：2004-06-29
申请号：US10215342
申请日：2002-08-09
申请人： Jin-Hwa Heo , Soo-Jin Hong
发明人： Jin-Hwa Heo , Soo-Jin Hong
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： The present invention is directed toward a structure and method by which trench isolation for a wide trench and a narrow trench formed in first and second regions of a substrate may be achieved without formation of a void in an isolation layer, a groove exposing an isolation layer, or an electrical bridge between gates in a subsequent process. A lower isolation layer is formed on the substrate in a first and second trench. The lower isolation layer is patterned to fill a lower region of the first trench, and an upper isolation pattern is formed to fill the second trench and a remainder of the first trench. An aspect ratio of first trench is reduced, thereby preventing the occurrence of a void in the upper isolation layer, or a gap between the upper isolation layer and the substrate.
摘要翻译：本发明涉及一种结构和方法，通过该结构和方法可以实现在衬底的第一和第二区域中形成的宽沟槽和窄沟槽的沟槽隔离，而不会在隔离层中形成空隙，露出隔离层，或在后续过程中门之间的电桥。在第一和第二沟槽中的衬底上形成下隔离层。图案化下部隔离层以填充第一沟槽的下部区域，并且形成上部隔离图案以填充第二沟槽和第一沟槽的其余部分。第一沟槽的纵横比减小，从而防止在上隔离层中发生空隙或上隔离层与基板之间的间隙。

4. 发明申请

US20110045647A1 METHODS OF FORMING NON-VOLATILE MEMORY DEVICES 有权
标题翻译：形成非易失性存储器件的方法
公开(公告)号：US20110045647A1
公开(公告)日：2011-02-24
申请号：US12916718
申请日：2010-11-01
申请人： Jin-Hwa Heo , Chul-Sung Kim , Bon-Young Koo , Ki-Hyun Hwang , Chang-Hyun Lee
发明人： Jin-Hwa Heo , Chul-Sung Kim , Bon-Young Koo , Ki-Hyun Hwang , Chang-Hyun Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28202 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/518
摘要： A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.
摘要翻译：非易失性存储器件包括电荷存储层和衬底之间的电介质层。可以减少电介质层的自由键，以减少/防止电荷通过游离键泄漏和/或被游离键捕获。结果，可以增强非挥发性存储器件的数据保持性能和/或耐久性。

5. 发明授权

US07160787B2 Structure of trench isolation and a method of forming the same 有权
标题翻译：沟槽隔离结构及其形成方法
公开(公告)号：US07160787B2
公开(公告)日：2007-01-09
申请号：US10791740
申请日：2004-03-04
申请人： Jin-Hwa Heo , Soo-Jin Hong
发明人： Jin-Hwa Heo , Soo-Jin Hong
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： The present invention is directed toward a structure and method by which trench isolation for a wide trench and a narrow trench formed in first and second regions of a substrate may be achieved without formation of a void in an isolation layer, a groove exposing an isolation layer, or an electrical bridge between gates in a subsequent process. A lower isolation layer is formed on the substrate in a first and second trench. The lower isolation layer is patterned to fill a lower region of the first trench, and an upper isolation pattern is formed to fill the second trench and a remainder of the first trench. An aspect ratio of first trench is reduced, thereby preventing the occurrence of a void in the upper isolation layer, or a gap between the upper isolation layer and the substrate.
摘要翻译：本发明涉及一种结构和方法，通过该结构和方法可以实现在衬底的第一和第二区域中形成的宽沟槽和窄沟槽的沟槽隔离，而不会在隔离层中形成空隙，露出隔离层，或在后续过程中门之间的电桥。在第一和第二沟槽中的衬底上形成下隔离层。图案化下部隔离层以填充第一沟槽的下部区域，并且形成上部隔离图案以填充第二沟槽和第一沟槽的其余部分。第一沟槽的纵横比减小，从而防止在上隔离层中发生空隙或上隔离层与基板之间的间隙。

6. 发明授权

US07141456B2 Methods of fabricating Fin-field effect transistors (Fin-FETs) having protection layers 有权
标题翻译：制造具有保护层的Fin场效应晶体管（Fin-FET）的方法
公开(公告)号：US07141456B2
公开(公告)日：2006-11-28
申请号：US10871742
申请日：2004-06-18
申请人： Deok-Hyung Lee , Si-Young Choi , Byeong-Chan Lee , In-Soo Jung , Jin-Hwa Heo
发明人： Deok-Hyung Lee , Si-Young Choi , Byeong-Chan Lee , In-Soo Jung , Jin-Hwa Heo
IPC分类号： H01L21/84 , H01L21/332
CPC分类号： H01L29/7851 , H01L29/66795
摘要： Methods for fabricating Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is formed on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is formed in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is formed on the first insulation layer and a second insulation layer is formed on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin. Related Fin-FETs are also provided.
摘要翻译：提供制造鳍场效应晶体管（Fin-FET）的方法。翅片形成在集成电路基板上。翅片限定集成电路基板上的沟槽。第一绝缘层形成在沟槽中，使得第一绝缘层的表面在鳍片的暴露在翅片的侧壁的表面下方凹进。保护层形成在第一绝缘层上，并且第二绝缘层形成在沟槽中的保护层上，使得保护层位于第二绝缘层和鳍的侧壁之间。还提供了相关的Fin-FET。

7. 发明申请

US20050285162A1 Semiconductor devices having a stacked structure and methods of forming the same 审中-公开
标题翻译：具有堆叠结构的半导体器件及其形成方法
公开(公告)号：US20050285162A1
公开(公告)日：2005-12-29
申请号：US11159596
申请日：2005-06-23
申请人： Chul-Sung Kim , Jin-Hwa Heo , Yu-Gyun Shin , Bon-Young Koo , Dong-Chan Kim , Jeong-Do Ryu
发明人： Chul-Sung Kim , Jin-Hwa Heo , Yu-Gyun Shin , Bon-Young Koo , Dong-Chan Kim , Jeong-Do Ryu
IPC分类号： H01L21/8244 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L29/78
CPC分类号： H01L27/0688 , H01L21/8221
摘要： Methods of forming a semiconductor device having stacked structures include forming a first semiconductor structure on a substrate and forming a first interlayer insulating layer on the substrate. The first interlayer insulating layer has a substantially level upper face. A semiconductor layer is formed on the first interlayer insulating layer and a first gate insulation layer is formed on the semiconductor layer at a processing temperature selected to control damage to the first semiconductor structure. A second semiconductor structure is formed on the first gate insulation layer.
摘要翻译：形成具有堆叠结构的半导体器件的方法包括在衬底上形成第一半导体结构并在衬底上形成第一层间绝缘层。第一层间绝缘层具有基本上平坦的上表面。在第一层间绝缘层上形成半导体层，在半导体层上形成第一栅极绝缘层，该处理温度被选择为控制第一半导体结构的损坏。在第一栅绝缘层上形成第二半导体结构。

8. 发明授权

US06593207B2 Method of forming a trench device isolation structure with upper liner pattern 失效
标题翻译：形成具有上衬垫图案的沟槽器件隔离结构的方法
公开(公告)号：US06593207B2
公开(公告)日：2003-07-15
申请号：US10121862
申请日：2002-04-15
申请人： Soo-Jin Hong , Jin-Hwa Heo
发明人： Soo-Jin Hong , Jin-Hwa Heo
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method of forming a trench device isolation structure, wherein, after forming a trench in a predetermined area of a semiconductor substrate, a lower isolation pattern, an upper liner pattern, and an upper isolation pattern are sequentially formed to fill the trench. A lower device isolation layer is formed on an entire surface of the semiconductor substrate, and then etched to form the lower isolation pattern so that a top surface of the lower isolation pattern is lower than a top surface of the semiconductor substrate. An upper liner layer and an upper device isolation layer are formed on the entire surface of the semiconductor substrate including the lower isolation pattern, and then etched to form the upper liner pattern. As a result, the upper liner pattern covers the top surface of the lower isolation pattern and surrounds the bottom and the sidewall of the upper isolation pattern.
摘要翻译：一种形成沟槽器件隔离结构的方法，其中，在半导体衬底的预定区域中形成沟槽之后，依次形成下隔离图案，上衬垫图案和上隔离图案以填充沟槽。在半导体衬底的整个表面上形成下部器件隔离层，然后蚀刻以形成下部隔离图案，使得下部隔离图案的顶表面低于半导体衬底的顶表面。在包括下隔离图案的半导体衬底的整个表面上形成上衬层和上器件隔离层，然后蚀刻以形成上衬垫图案。结果，上衬垫图案覆盖下隔离图案的顶表面并且围绕上隔离图案的底部和侧壁。

9. 发明授权

US06566229B2 Method of forming an insulating layer in a trench isolation type semiconductor device 失效
公开(公告)号：US06566229B2
公开(公告)日：2003-05-20
申请号：US09991928
申请日：2001-11-26
申请人： Soo-Jin Hong , Moon-Han Park , Ju-Seon Goo , Jin-Hwa Heo , Hong-Gun Kim , Eun-Kee Hong
发明人： Soo-Jin Hong , Moon-Han Park , Ju-Seon Goo , Jin-Hwa Heo , Hong-Gun Kim , Eun-Kee Hong
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method of forming a trench-type device isolation layer in which a trench is filled through two steps, wherein a polysilazane solution is coated on a semiconductor substrate, in which a trench for device isolation layer is formed, in a spin on glass (SOG) manner to form an SOG layer filling a predetermined portion of the trench. In order to maintain a conformal coating thickness without overfilling the trench, the polysilazane solution preferably has a solid-state perhydro polysilazane ([SiH2NH]n) of between about 5 to about 15 percent by weight. Following formation of the SOG layer, a subsequent annealing process is carried out. The SOG layer is etched to make a top surface of the remaining SOG layer recessed down to a degree of about 1000 Å from an inlet of the trench, and a remaining space of the trench is filled with an ozone TEOS USG layer or an HDP CVD layer.

10. 发明授权

US08008154B2 Methods of forming impurity containing insulating films and flash memory devices including the same 失效
标题翻译：形成含杂质的绝缘膜的方法和包括其的闪存器件的方法
公开(公告)号：US08008154B2
公开(公告)日：2011-08-30
申请号：US12188482
申请日：2008-08-08
申请人： Young-Jin Noh , Bon-Young Koo , Si-Young Choi , Ki-Hyun Hwang , Chul-Sung Kim , Sung-Kweon Baek , Jin-Hwa Heo
发明人： Young-Jin Noh , Bon-Young Koo , Si-Young Choi , Ki-Hyun Hwang , Chul-Sung Kim , Sung-Kweon Baek , Jin-Hwa Heo
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L21/0214 , H01L21/02238 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/28273 , H01L21/3145 , H01L21/31662
摘要： Methods of forming an insulating film include forming an insulating film on a substrate. A first impurity is injected into the insulating film using a thermal process under a first set of processing conditions to form a first impurity concentration peak in a lower portion of the insulating film. A second impurity is injected into the insulating film using the thermal process under a second set of processing conditions, different from the first set of processing conditions, to form a second impurity concentration peak in an upper portion of the insulating film. Injecting the first impurity and injecting the second impurity may be carried out without using plasma and the first impurity concentration peak may be higher than the second impurity concentration peak.
摘要翻译：形成绝缘膜的方法包括在基板上形成绝缘膜。使用第一组处理条件下的热处理将第一杂质注入绝缘膜，以在绝缘膜的下部形成第一杂质浓度峰。在与第一组处理条件不同的第二组处理条件下，使用热处理将第二杂质注入到绝缘膜中，以在绝缘膜的上部形成第二杂质浓度峰。注入第一杂质并注入第二杂质可以在不使用等离子体的情况下进行，并且第一杂质浓度峰可以高于第二杂质浓度峰。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式