专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08859302B2 Structure and method for adjusting threshold voltage of the array of transistors 有权
标题翻译：用于调整晶体管阵列的阈值电压的结构和方法
公开(公告)号：US08859302B2
公开(公告)日：2014-10-14
申请号：US13036243
申请日：2011-02-28
申请人： Ali Khakifirooz , Jin Cai , Kangguo Cheng , Robert H. Dennard , Tak H. Ning
发明人： Ali Khakifirooz , Jin Cai , Kangguo Cheng , Robert H. Dennard , Tak H. Ning
IPC分类号： H01L21/66 , G11C11/412 , H01L27/11 , H01L27/12 , H01L21/84 , H01L27/115 , H01L29/66
CPC分类号： G11C11/418 , G11C11/412 , G11C11/419 , G11C29/50004 , G11C2029/5004 , G11C2029/5006 , H01L21/84 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/11568 , H01L27/1203 , H01L29/0603 , H01L29/66833 , H01L29/786 , H01L29/792
摘要： A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.
摘要翻译：一种半导体器件，包括存在于其上形成有半导体器件的衬底的埋置介质层中的电荷存储元件。可以使用电荷注入来将电荷引入存在于衬底内的掩埋介电层的电荷存储元件。注入电荷存储元件的电荷可用于调整存在于基板上的半导体器件阵列内的每个半导体器件的阈值电压（Vt）。

2. 发明授权

US08766410B2 Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors 有权
标题翻译：嵌入式DRAM集成电路，具有极薄的绝缘体上硅传导晶体管
公开(公告)号：US08766410B2
公开(公告)日：2014-07-01
申请号：US13153806
申请日：2011-06-06
申请人： Jin Cai , Josephine Chang , Leland Chang , Brian L. Ji , Steven John Koester , Amlan Majumdar
发明人： Jin Cai , Josephine Chang , Leland Chang , Brian L. Ji , Steven John Koester , Amlan Majumdar
IPC分类号： H01L23/58
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10894
摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
摘要翻译：提供具有组合的存储器和逻辑功能的集成电路。一方面，提供集成电路。集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。

3. 发明授权

US08558282B1 Germanium lateral bipolar junction transistor 有权
公开(公告)号：US08558282B1
公开(公告)日：2013-10-15
申请号：US13607672
申请日：2012-09-08
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Bahman Hekmatshoartabari , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Bahman Hekmatshoartabari , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L21/331
CPC分类号： H01L29/6625 , H01L29/161 , H01L29/735
摘要： A germanium lateral bipolar junction transistor (BJT) is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap contact for minority carriers is provided between the silicon base region and the germanium base region and between the silicon emitter region and the germanium emitter region.

4. 发明申请

US20130260526A1 SOI LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING A WIDE BAND GAP EMITTER CONTACT 有权
公开(公告)号：US20130260526A1
公开(公告)日：2013-10-03
申请号：US13605253
申请日：2012-09-06
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L21/8222
CPC分类号： H01L29/42304 , H01L29/66242 , H01L29/66272 , H01L29/7322 , H01L29/7371
摘要： A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.

5. 发明授权

US08526220B2 Complementary SOI lateral bipolar for SRAM in a low-voltage CMOS platform 有权
标题翻译：在低电压CMOS平台中用于SRAM的互补SOI横向双极性
公开(公告)号：US08526220B2
公开(公告)日：2013-09-03
申请号：US13158420
申请日：2011-06-12
申请人： Jin Cai , Tak H. Ning
发明人： Jin Cai , Tak H. Ning
IPC分类号： G11C11/00
CPC分类号： H01L27/082 , G11C11/41 , G11C11/411 , G11C11/412 , H01L21/8228 , H01L21/84 , H01L27/1023 , H01L27/1203
摘要： An example embodiment is a memory cell including a SOI substrate. A first and second set of lateral bipolar transistors are fabricated on the SOI substrate. The first and second set of lateral bipolar transistors are electrically coupled to form two inverters. The inverters are cross coupled to form a memory element.
摘要翻译：示例性实施例是包括SOI衬底的存储单元。在SOI衬底上制造第一和第二组横向双极晶体管。第一和第二组横向双极晶体管电耦合以形成两个反相器。逆变器交叉耦合以形成存储元件。

6. 发明申请

US20130168821A1 SOI LATERAL BIPOLAR TRANSISTOR HAVING MULTI-SIDED BASE CONTACT AND METHODS FOR MAKING SAME 有权
标题翻译：具有多面基底接触的SOI侧向双极晶体管及其制造方法
公开(公告)号：US20130168821A1
公开(公告)日：2013-07-04
申请号：US13343688
申请日：2012-01-04
申请人： Jin Cai , Tak H. Ning
发明人： Jin Cai , Tak H. Ning
IPC分类号： H01L27/082 , H01L21/328 , H01L29/70
CPC分类号： H01L27/082 , H01L21/8249 , H01L29/1004 , H01L29/42304 , H01L29/45 , H01L29/6625 , H01L29/735
摘要： A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT.
摘要翻译：一种具有本征基极的双极结晶体管，其中本征基极包括顶表面和与顶表面正交的两个侧壁，以及电耦合到本征基底的侧壁的基部接触。在一个实施例中，装置可以包括多个双极结晶体管，以及电耦合到每个BJT的内部基极的侧壁的基部触点。

7. 发明授权

US08445356B1 Integrated circuit having back gating, improved isolation and reduced well resistance and method to fabricate same 有权
标题翻译：集成电路具有后门控，改进的隔离和降低的阱电阻以及制造相同的方法
公开(公告)号：US08445356B1
公开(公告)日：2013-05-21
申请号：US13343819
申请日：2012-01-05
申请人： Jin Cai , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Jin Cai , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/76
CPC分类号： H01L29/0649 , H01L21/76232 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： Disclosed is a method of forming a structure and a resulting structure. The method includes providing a semiconductor substrate; forming a first opening to a first depth in the semiconductor substrate; amorphizing semiconductor sidewalls of an upper portion of the first opening leaving unamorphized semiconductor sidewalls in a lower portion of the first opening; enlarging only the lower portion of the first opening using an etch process that is selective to the unamorphized semiconductor sidewalls; filling the first opening with an insulator material to form a deep trench isolation (DTI) structure and implanting a first well region and a second well region into the semiconductor substrate. The first well and the second well are separated from one another by the enlarged lower portion of the first opening. In the structure sidewalls of a top portion of a DTI and sidewalls of an STI are formed of doped, re-crystallized silicon.
摘要翻译：公开了一种形成结构和所得结构的方法。该方法包括：提供半导体衬底; 在所述半导体衬底中形成第一深度的第一开口; 将第一开口的上部的半导体侧壁非晶化，在第一开口的下部离开未变形的半导体侧壁; 使用对未变形的半导体侧壁具有选择性的蚀刻工艺仅扩大第一开口的下部; 用绝缘体材料填充第一开口以形成深沟槽隔离（DTI）结构，并将第一阱区域和第二阱区域注入到半导体衬底中。第一孔和第二孔通过第一开口的扩大的下部彼此分开。在DTI的顶部部分和STI侧壁中的结构中，由掺杂的再结晶硅形成。

8. 发明申请

US20120314485A1 COMPLEMENTARY SOI LATERAL BIPOLAR FOR SRAM IN A LOW-VOLTAGE CMOS PLATFORM 有权
标题翻译：用于低电压CMOS平台的SRAM的补充SOI侧向双极性
公开(公告)号：US20120314485A1
公开(公告)日：2012-12-13
申请号：US13158420
申请日：2011-06-12
申请人： Jin Cai , Tak H. Ning
发明人： Jin Cai , Tak H. Ning
IPC分类号： G11C11/34 , H01L21/8222 , G11C11/00
CPC分类号： H01L27/082 , G11C11/41 , G11C11/411 , G11C11/412 , H01L21/8228 , H01L21/84 , H01L27/1023 , H01L27/1203
摘要： An example embodiment is a memory cell including a SOI substrate. A first and second set of lateral bipolar transistors are fabricated on the SOI substrate. The first and second set of lateral bipolar transistors are electrically coupled to form two inverters. The inverters are cross coupled to form a memory element.
摘要翻译：示例性实施例是包括SOI衬底的存储单元。在SOI衬底上制造第一和第二组横向双极晶体管。第一和第二组横向双极晶体管电耦合以形成两个反相器。逆变器交叉耦合以形成存储元件。

9. 外观设计

USD672077S1 LED lamp 有权
公开(公告)号：USD672077S1
公开(公告)日：2012-12-04
申请号：US29415151
申请日：2012-03-08
申请人： Qian-Jin Cai , You-Xue Liu
设计人： Qian-Jin Cai , You-Xue Liu

10. 发明申请

US20120299104A1 SCHOTTKY FET FABRICATED WITH GATE LAST PROCESS 有权
标题翻译： SCHOTTKY FET采用上盖工艺制作
公开(公告)号：US20120299104A1
公开(公告)日：2012-11-29
申请号：US13571429
申请日：2012-08-10
申请人： Jin Cai , Dechao Guo , Marwan H. Khater , Christian Lavoie , Zhen Zhang
发明人： Jin Cai , Dechao Guo , Marwan H. Khater , Christian Lavoie , Zhen Zhang
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/665 , H01L29/66545 , H01L29/66621
摘要： A field effect transistor (FET) includes a semiconductor on insulator substrate, the substrate comprising a top semiconductor layer; source and drain regions located in the top semiconductor layer; a channel region located in the top semiconductor layer between the source region and the drain region, the channel region having a thickness that is less than a thickness of the source and drain regions; a gate located over the channel region; and a supporting material located over the source and drain regions adjacent to the gate.
摘要翻译：场效应晶体管（FET）包括绝缘体上半导体衬底，所述衬底包括顶部半导体层; 源极和漏极区域位于顶部半导体层中; 位于源极区域和漏极区域之间的顶部半导体层中的沟道区域，沟道区域的厚度小于源极和漏极区域的厚度; 位于通道区域上方的门; 以及位于与栅极相邻的源极和漏极区域之上的支撑材料。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式