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1. 发明授权

US08253405B2 High speed voltage regulator with integrated loseless current sensing 有权
标题翻译：具有集成无电流电流检测功能的高速电压调节器
公开(公告)号：US08253405B2
公开(公告)日：2012-08-28
申请号：US12347711
申请日：2008-12-31
申请人： Malay Trivedi , Jiang William , Brent D. Thomas , James T. Doyle , Rose Wang
发明人： Malay Trivedi , Jiang William , Brent D. Thomas , James T. Doyle , Rose Wang
IPC分类号： G05F1/00
CPC分类号： G06F1/26
摘要： In general, in one aspect, the disclosure describes a high-speed multi-phase voltage regulator (VR) capable of sensing load current. For each phase leg, the VR includes a current mirror to mirror current in switching elements, a current sense to sense high side current in the current mirror, and a I-V converter to convert the sensed high side current to a voltage. The high side sensed current for each phase leg is averaged and the duty cycle for the VR is extracted. The average high side sensed current and the duty cycle are converted to digital by an A-D converter. Digital circuitry corrects the sensed current by adjusting for the gain and offset voltage of the VR. The adjusted sensed value is divided by the duty cycle to convert to load current and the average load current is multiplied by the number of phases operating to determine overall load current.
摘要翻译：通常，一方面，本公开描述了能够感测负载电流的高速多相电压调节器（VR）。对于每个相支路，VR包括用于在开关元件中镜像电流的电流镜，用于感测电流镜中的高侧电流的电流感测，以及将感测到的高侧电流转换为电压的I-V转换器。对每个相位支路的高侧检测电流进行平均，并提取VR的占空比。平均高侧检测电流和占空比由A-D转换器转换为数字。数字电路通过调整VR的增益和失调电压来校正感测电流。调整后的感测值除以占空比转换为负载电流，平均负载电流乘以确定总负载电流的相位数。

2. 发明申请

US20100164477A1 HIGH SPEED VOLTAGE REGULATOR WITH INTEGRATED LOSELESS CURRENT SENSING 有权
标题翻译：具有集成无电流电流传感的高速电压调节器
公开(公告)号：US20100164477A1
公开(公告)日：2010-07-01
申请号：US12347711
申请日：2008-12-31
申请人： Malay Trivedi , Jiang William , Brent D. Thomas , James T. Doyle , Rose Wang
发明人： Malay Trivedi , Jiang William , Brent D. Thomas , James T. Doyle , Rose Wang
IPC分类号： G01R19/00 , G05F1/10
CPC分类号： G06F1/26
摘要： In general, in one aspect, the disclosure describes a high-speed multi-phase voltage regulator (VR) capable of sensing load current. For each phase leg, the VR includes a current mirror to mirror current in switching elements, a current sense to sense high side current in the current mirror, and a I-V converter to convert the sensed high side current to a voltage. The high side sensed current for each phase leg is averaged and the duty cycle for the VR is extracted. The average high side sensed current and the duty cycle are converted to digital by an A-D converter. Digital circuitry corrects the sensed current by adjusting for the gain and offset voltage of the VR. The adjusted sensed value is divided by the duty cycle to convert to load current and the average load current is multiplied by the number of phases operating to determine overall load current.
摘要翻译：通常，一方面，本公开描述了能够感测负载电流的高速多相电压调节器（VR）。对于每个相支路，VR包括用于在开关元件中镜像电流的电流镜，用于感测电流镜中的高侧电流的电流感测，以及将感测到的高侧电流转换为电压的I-V转换器。对每个相位支路的高侧检测电流进行平均，并提取VR的占空比。平均高侧检测电流和占空比由A-D转换器转换为数字。数字电路通过调整VR的增益和失调电压来校正感测电流。调整后的感测值除以占空比转换为负载电流，平均负载电流乘以确定总负载电流的相位数。

3. 发明申请

US20100033236A1 PACKAGED VOLTAGE REGULATOR AND INDUCTOR ARRAY 有权
标题翻译：包装电压调节器和电感器阵列
公开(公告)号：US20100033236A1
公开(公告)日：2010-02-11
申请号：US11968115
申请日：2007-12-31
申请人： Nicholas D. TRIANTAFILLOU , Malay TRIVEDI , Erik A. MCSHANE , James T. DOYLE , Mark J. KACHMAREK
发明人： Nicholas D. TRIANTAFILLOU , Malay TRIVEDI , Erik A. MCSHANE , James T. DOYLE , Mark J. KACHMAREK
IPC分类号： G05F1/10 , H01L27/06 , H01L21/50
CPC分类号： H01L23/645 , H01F2017/0086 , H01L2224/16227 , H01L2224/16265 , H01L2924/0002 , H01L2924/19103 , H01L2924/19104 , H01L2924/3011 , H01L2924/00
摘要： Inductors packaged with a voltage regulator for an integrated circuit within the same package are deposited to a sufficient thickness to reduce resistance and improve the quality factor. Furthermore, the voltage regulator switches currents through the inductors at a relatively high frequency such that the overall size and inductances of the inductors may be reduced. As a consequence, integrating both the integrated circuits including a voltage regulator and associated inductor array in a single package is facilitated. Other embodiments are described and claimed.
摘要翻译：与同一封装内的集成电路的电压调节器封装的电感器被沉积到足够的厚度以降低电阻并提高品质因数。此外，电压调节器以相对高的频率切换电流通过电感器，使得可以减小电感器的总体尺寸和电感。因此，将包括电压调节器和相关联的电感器阵列的集成电路集成在单个封装中是便利的。描述和要求保护其他实施例。

4. 发明授权

US06771101B1 CMOS reference circuit using field effect transistors in lieu of resistors and diodes 有权
标题翻译： CMOS参考电路采用场效应晶体管代替电阻和二极管
公开(公告)号：US06771101B1
公开(公告)日：2004-08-03
申请号：US10226523
申请日：2002-08-22
申请人： James T. Doyle
发明人： James T. Doyle
IPC分类号： H03L700
CPC分类号： G05F3/30 , Y10S323/901
摘要： A CMOS reference circuit using field effect transistors (FETs) is described. A first plurality of FETs is coupled in series, source node to drain node. A second plurality of FETs is also coupled in series, source node to drain node. The first and second plurality of FETs are coupled such that a specified total voltage drop across the first plurality of FETs is realizable. The combination of the first and second plurality of FETs are usable as a replacement for a resistor. The circuit can also include a FET configured so that it is usable as a replacement for a diode.
摘要翻译：描述了使用场效应晶体管（FET）的CMOS参考电路。第一组多个FET串联耦合，源节点到漏极节点。第二组多个FET串联耦合，源节点到漏极节点。第一和第二多个FET被耦合，使得跨越第一多个FET的规定的总电压降是可实现的。第一和第二多个FET的组合可用作电阻器的替代。该电路还可以包括被配置为使得其可用作二极管的替代物的FET。

5. 发明授权

US06629254B1 Clocking architecture to compensate a delay introduced by a signal buffer 有权
标题翻译：时钟架构来补偿由信号缓冲器引入的延迟
公开(公告)号：US06629254B1
公开(公告)日：2003-09-30
申请号：US09607565
申请日：2000-06-29
申请人： Syed R. Naqvi , James T. Doyle
发明人： Syed R. Naqvi , James T. Doyle
IPC分类号： G06F112
CPC分类号： H03L7/0812 , G06F1/10 , H03L7/06
摘要： An apparatus includes a memory buffer, a first signal buffer, a locked loop circuit and a feedback circuit. The memory buffer provides a data signal to an output terminal of the memory buffer in response to a first clock signal. The first signal buffer is coupled between the output terminal of the memory buffer and a data line of a bus. The first signal buffer introduces a first delay. The locked loop circuit furnishes the first clock signal to establish a predefined relationship between a phase of a second clock signal and a phase of a third clock signal. The feedback circuit produces the second clock signal in response to the first clock signal. The feedback circuit includes a second signal buffer to introduce a second delay to the second clock, and the second delay is approximately the same as the first delay that is introduced by the first signal buffer.
摘要翻译：一种装置包括存储器缓冲器，第一信号缓冲器，锁定环路电路和反馈电路。存储器缓冲器响应于第一时钟信号向存储器缓冲器的输出端提供数据信号。第一信号缓冲器耦合在存储器缓冲器的输出端和总线的数据线之间。第一个信号缓冲器引入第一个延迟。锁定环路电路提供第一时钟信号以建立第二时钟信号的相位和第三时钟信号的相位之间的预定关系。反馈电路响应于第一时钟信号产生第二时钟信号。反馈电路包括用于向第二时钟引入第二延迟的第二信号缓冲器，并且第二延迟与由第一信号缓冲器引入的第一延迟大致相同。

6. 发明授权

US6147548A Sub-bandgap reference using a switched capacitor averaging circuit 有权
标题翻译：使用开关电容平均电路的子带隙基准
公开(公告)号：US6147548A
公开(公告)日：2000-11-14
申请号：US441629
申请日：1999-11-16
申请人： James T. Doyle
发明人： James T. Doyle
IPC分类号： G05F3/30 , G05F1/10
CPC分类号： G05F3/30
摘要： A sub-bandgap reference circuit yielding a reference voltage smaller than the bandgap voltage of silicon. The circuit generates a negative temperature coefficient signal V.sub.be and an oppositely tracking (positive temperature coefficient) .DELTA.V.sub.be, and takes the average of two signals related to .DELTA.V.sub.be -V.sub.be to yield a temperature-compensated voltage of one-half the bandgap voltage of silicon. The circuit features an unequal area current mirror feeding the diodes and resistors used to generate the .DELTA.V.sub.be -V.sub.be signals using low supply voltages (less than 1.5 volts). A standard CMOS implementation provides low power consumption at a supply voltage of only 1 volt with a good temperature coefficient. The averaging circuit may be implemented by a continuous time divider or by using switched capacitor techniques. The loop amplifier used in the .DELTA.V.sub.be -V.sub.be circuitry operates with low headroom in part due to a n-well biasing scheme that lowers the effective threshold voltage of the p-channel FETs used in the loop amplifier.
摘要翻译：产生比硅的带隙电压小的参考电压的子带隙参考电路。电路产生负温度系数信号Vbe和相反的跟踪（正温度系数）DELTA Vbe，并且获得与DELTA Vbe-Vbe相关的两个信号的平均值，以得到硅的带隙电压的一半的温度补偿电压。该电路具有不等面积的电流镜，馈送用于使用低电源电压（小于1.5伏）产生DELTA Vbe-Vbe信号的二极管和电阻。标准CMOS实现在仅1伏特的电源电压和良好的温度系数下提供低功耗。平均电路可以由连续时分器或通过使用开关电容器技术来实现。在DELTA Vbe-Vbe电路中使用的环路放大器部分由于采用n阱偏置方案，具有较低的余量运行，降低了环路放大器中使用的p沟道FET的有效阈值电压。

7. 发明授权

US06069503A High value FET resistors on a submicron MOS technology 失效
标题翻译：亚微米MOS技术上的高价值FET电阻
公开(公告)号：US06069503A
公开(公告)日：2000-05-30
申请号：US38807
申请日：1998-03-11
申请人： James T. Doyle
发明人： James T. Doyle
IPC分类号： H03K17/687 , H03K3/01
CPC分类号： H03K17/6874
摘要： A method and apparatus of biasing a transistor to perform as a resistive device in an integrated circuit die is disclosed. A base lead of a transistor is coupled to a first lead of the transistor. A voltage is applied to a first lead such that the voltage does not exceed a threshold voltage of the transistor.
摘要翻译：公开了一种偏置晶体管以在集成电路管芯中作为电阻器件实现的方法和装置。晶体管的基极引线耦合到晶体管的第一引线。电压施加到第一引线，使得电压不超过晶体管的阈值电压。

8. 发明授权

US5856980A Baseband encoding method and apparatus for increasing the transmission rate over a communication medium 失效
标题翻译：用于增加通信介质上的传输速率的基带编码方法和装置
公开(公告)号：US5856980A
公开(公告)日：1999-01-05
申请号：US351695
申请日：1994-12-08
申请人： James T. Doyle
发明人： James T. Doyle
IPC分类号： H03M5/20 , H03M13/31 , H04L25/49 , G06F11/00
CPC分类号： H03M5/20 , H03M13/31 , H04L25/4919
摘要： An encoder for encoding binary data bits supplied by a data source into pulse amplitude modulated multilevel symbols. The encoder includes a bit stuffer for receiving the data bits from the data source at a first data bit rate, which at most equals a maximum data bit rate. The bit stuffer then adds descriptive bits to the data bits at a descriptive bit rate, which at most equals a maximum descriptive bit rate. The encoder also includes a multilevel pulse amplitude modulator for receiving the data and descriptive bits from the bit stuffer and for converting the data and descriptive bits into pulse amplitude modulated multilevel symbols. When these multilevel PAM symbols are transmitted, they have a spectral energy characteristic which is below a predetermined low level threshold at a predetermined baseband bandwidth frequency. In addition, these multilevel PAM symbols have a symbol rate (i.e., baud rate) which at most equals a maximum baud rate when the first data bit rate equals the maximum data bit rate and the descriptive bit rate equals the maximum descriptive bit rate. In turn, the magnitude of the maximum baud rate equals the magnitude of the baseband bandwidth frequency.
摘要翻译：用于将由数据源提供的二进制数据位编码成脉冲幅度调制多电平符号的编码器。编码器包括位填充器，用于以最多等于最大数据比特率的第一数据比特率从数据源接收数据比特。位填充器然后以描述性比特率向数据位添加描述性位，其最多等于最大描述比特率。编码器还包括一个多电平脉冲幅度调制器，用于从位填充器接收数据和描述位，并将数据和描述位转换为脉冲调幅多电平符号。当发送这些多电平PAM符号时，它们具有在预定基带带宽频率下低于预定低电平阈值的频谱能量特性。此外，当第一数据比特率等于最大数据比特率并且描述比特率等于最大描述比特率时，这些多级PAM符号具有最多等于最大波特率的符号速率（即，波特率）。反过来，最大波特率的大小等于基带带宽频率的幅度。

9. 发明授权

US5841821A Bi-directional low pass filtering method and apparatus 失效
标题翻译：双向低通滤波方法及装置
公开(公告)号：US5841821A
公开(公告)日：1998-11-24
申请号：US764513
申请日：1996-12-12
申请人： James T. Doyle , Carl F. Liepold
发明人： James T. Doyle , Carl F. Liepold
IPC分类号： H03F3/45 , H03H7/01 , H03H11/04 , H04L5/16 , H04L25/03 , H04B1/10
CPC分类号： H03H7/1766 , H03F3/45085 , H03H11/045 , H03H7/0115 , H04L25/03343 , H04L5/16 , H03F2203/45371 , H03F2203/45574 , H03F2203/45612
摘要： The present invention provides a bi-directional low pass filtering method and apparatus for attenuating out-of-baseband components of data transmitted from an encoder to a decoder over a transmission medium. In one embodiment of the present invention, the bi-directional low pass filtering apparatus includes a Chebyshev filter that has a first phase response. This Chebyshev filter is coupled to a phase correction circuit, which has a second phase response. This second phase response of the phase correction circuit is designed to oppose the first phase response in order to offset variations in group delay in the data due to the Chebyshev filter.
摘要翻译：本发明提供一种双向低通滤波方法和装置，用于通过传输介质衰减从编码器发送到解码器的数据的基带外分量。在本发明的一个实施例中，双向低通滤波装置包括具有第一相位响应的切比雪夫滤波器。该切比雪夫滤波器耦合到具有第二相位响应的相位校正电路。相位校正电路的第二相位响应被设计为与第一相位响应相反，以便抵消由切比雪夫滤波器引起的数据中组延迟的变化。

10. 发明授权

US5717716A Quasi-adaptive analog equalization method and apparatus 失效
标题翻译：准自适应模拟均衡方法和装置
公开(公告)号：US5717716A
公开(公告)日：1998-02-10
申请号：US414618
申请日：1995-03-31
申请人： James T. Doyle
发明人： James T. Doyle
IPC分类号： H03H7/30
CPC分类号： H04L25/0268
摘要： A quasi-adaptive analog equalization method and apparatus for compensating for phase and amplitude degradation of data transmitted over a transmission medium. One embodiment of the present invention includes a first quasi-adaptive equalizer that receives a first set of data, in order to adjust the amplitude and phase of the first set of data to produce a second set of data. The first quasi-adaptive equalizer then supplies the second set of data to a second quasi-adaptive equalizer, which adjusts the amplitude and phase of the second set of data to produce an equalized set of data. As both the first and the second equalizers are quasi-adaptive equalizers, they base the amount of their phase and amplitude compensation on the amplitude of the symbol pulses that the equalization network receives.
摘要翻译：一种准自适应模拟均衡方法和装置，用于补偿在传输介质上传输的数据的相位和幅度衰减。本发明的一个实施例包括接收第一组数据的第一准自适应均衡器，以便调整第一组数据的幅度和相位以产生第二组数据。然后，第一准自适应均衡器将第二组数据提供给第二准自适应均衡器，第二准自适应均衡器调整第二组数据的幅度和相位以产生均衡的数据集。由于第一和第二均衡器都是准自适应均衡器，它们的相位和幅度补偿量基于均衡网络接收到的符号脉冲的幅度。

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