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1. 发明授权

US08253405B2 High speed voltage regulator with integrated loseless current sensing 有权
标题翻译：具有集成无电流电流检测功能的高速电压调节器
公开(公告)号：US08253405B2
公开(公告)日：2012-08-28
申请号：US12347711
申请日：2008-12-31
申请人： Malay Trivedi , Jiang William , Brent D. Thomas , James T. Doyle , Rose Wang
发明人： Malay Trivedi , Jiang William , Brent D. Thomas , James T. Doyle , Rose Wang
IPC分类号： G05F1/00
CPC分类号： G06F1/26
摘要： In general, in one aspect, the disclosure describes a high-speed multi-phase voltage regulator (VR) capable of sensing load current. For each phase leg, the VR includes a current mirror to mirror current in switching elements, a current sense to sense high side current in the current mirror, and a I-V converter to convert the sensed high side current to a voltage. The high side sensed current for each phase leg is averaged and the duty cycle for the VR is extracted. The average high side sensed current and the duty cycle are converted to digital by an A-D converter. Digital circuitry corrects the sensed current by adjusting for the gain and offset voltage of the VR. The adjusted sensed value is divided by the duty cycle to convert to load current and the average load current is multiplied by the number of phases operating to determine overall load current.
摘要翻译：通常，一方面，本公开描述了能够感测负载电流的高速多相电压调节器（VR）。对于每个相支路，VR包括用于在开关元件中镜像电流的电流镜，用于感测电流镜中的高侧电流的电流感测，以及将感测到的高侧电流转换为电压的I-V转换器。对每个相位支路的高侧检测电流进行平均，并提取VR的占空比。平均高侧检测电流和占空比由A-D转换器转换为数字。数字电路通过调整VR的增益和失调电压来校正感测电流。调整后的感测值除以占空比转换为负载电流，平均负载电流乘以确定总负载电流的相位数。

2. 发明申请

US20100164477A1 HIGH SPEED VOLTAGE REGULATOR WITH INTEGRATED LOSELESS CURRENT SENSING 有权
标题翻译：具有集成无电流电流传感的高速电压调节器
公开(公告)号：US20100164477A1
公开(公告)日：2010-07-01
申请号：US12347711
申请日：2008-12-31
申请人： Malay Trivedi , Jiang William , Brent D. Thomas , James T. Doyle , Rose Wang
发明人： Malay Trivedi , Jiang William , Brent D. Thomas , James T. Doyle , Rose Wang
IPC分类号： G01R19/00 , G05F1/10
CPC分类号： G06F1/26
摘要： In general, in one aspect, the disclosure describes a high-speed multi-phase voltage regulator (VR) capable of sensing load current. For each phase leg, the VR includes a current mirror to mirror current in switching elements, a current sense to sense high side current in the current mirror, and a I-V converter to convert the sensed high side current to a voltage. The high side sensed current for each phase leg is averaged and the duty cycle for the VR is extracted. The average high side sensed current and the duty cycle are converted to digital by an A-D converter. Digital circuitry corrects the sensed current by adjusting for the gain and offset voltage of the VR. The adjusted sensed value is divided by the duty cycle to convert to load current and the average load current is multiplied by the number of phases operating to determine overall load current.
摘要翻译：通常，一方面，本公开描述了能够感测负载电流的高速多相电压调节器（VR）。对于每个相支路，VR包括用于在开关元件中镜像电流的电流镜，用于感测电流镜中的高侧电流的电流感测，以及将感测到的高侧电流转换为电压的I-V转换器。对每个相位支路的高侧检测电流进行平均，并提取VR的占空比。平均高侧检测电流和占空比由A-D转换器转换为数字。数字电路通过调整VR的增益和失调电压来校正感测电流。调整后的感测值除以占空比转换为负载电流，平均负载电流乘以确定总负载电流的相位数。

3. 发明申请

US20100164622A1 SINGLE-ENDED TO DIFFERENTIAL AMPLIFICATION AND PIPELINE ANALOG-TO-DIGITAL CONVERSION FOR DIGITALLY CONTROLLED DC-DC CONVERTERS 有权
标题翻译：用于数字控制DC-DC转换器的差分放大和管线模拟数字转换
公开(公告)号：US20100164622A1
公开(公告)日：2010-07-01
申请号：US12347081
申请日：2008-12-31
申请人： Fuding Ge , Brent D. Thomas , Malay Trivedi , James T. Doyle
发明人： Fuding Ge , Brent D. Thomas , Malay Trivedi , James T. Doyle
IPC分类号： H03F3/45
CPC分类号： H03F3/005 , H03F3/45475
摘要： Methods and systems to amplify and convert a single-ended analog signal to a differential signal and to convert the differential signal to a digital value, including to time-multiplex a plurality of windowed single-ended analog error signals, amplify a difference between the time-multiplexed analog signals, sample a corresponding amplified difference signal and an inverted amplified difference signal, amplify and center the samples about a common mode, and convert a corresponding amplified differential signal to digital values in a pipeline fashion. Bias adjustable features may be implemented to control a bandwidth, and clock rates may be adjustable to correspond to the bandwidth.
摘要翻译：将单端模拟信号放大并转换为差分信号并将差分信号转换为数字值的方法和系统，包括对多个窗口化的单端模拟误差信号进行时间复用，放大时间差多路复用模拟信号，对相应的放大差分信号和反相放大差分信号进行采样，对共模进行放大和中心采样，并以相应的方式将相应的放大差分信号转换为数字值。可以实施偏置可调特征以控制带宽，并且时钟速率可以是可调节的以对应于带宽。

4. 发明授权

US07852252B2 Single-ended to differential amplification and pipeline analog-to-digital conversion for digitally controlled DC-DC converters 有权
标题翻译：用于数字控制DC-DC转换器的单端到差分放大和管线模数转换
公开(公告)号：US07852252B2
公开(公告)日：2010-12-14
申请号：US12347081
申请日：2008-12-31
申请人： Fuding Ge , Brent D. Thomas , Malay Trivedi , James T. Doyle
发明人： Fuding Ge , Brent D. Thomas , Malay Trivedi , James T. Doyle
IPC分类号： H03M1/12
CPC分类号： H03F3/005 , H03F3/45475
摘要： Methods and systems to amplify and convert a single-ended analog signal to a differential signal and to convert the differential signal to a digital value, including to time-multiplex a plurality of windowed single-ended analog error signals, amplify a difference between the time-multiplexed analog signals, sample a corresponding amplified difference signal and an inverted amplified difference signal, amplify and center the samples about a common mode, and convert a corresponding amplified differential signal to digital values in a pipeline fashion. Bias adjustable features may be implemented to control a bandwidth, and clock rates may be adjustable to correspond to the bandwidth.
摘要翻译：将单端模拟信号放大并转换为差分信号并将差分信号转换为数字值的方法和系统，包括对多个窗口化的单端模拟误差信号进行时间复用，放大时间差多路复用模拟信号，对相应的放大差分信号和反相放大差分信号进行采样，对共模进行放大和中心采样，并以相应的方式将相应的放大差分信号转换为数字值。可以实施偏置可调特征以控制带宽，并且时钟速率可以是可调节的以对应于带宽。

5. 发明申请

US20080238390A1 Dynamically adjusted multi-phase regulator 有权
标题翻译：动态调节多相调节器
公开(公告)号：US20080238390A1
公开(公告)日：2008-10-02
申请号：US11731161
申请日：2007-03-30
申请人： Malay Trivedi , Erik A. McShane , James T. Doyle
发明人： Malay Trivedi , Erik A. McShane , James T. Doyle
IPC分类号： G05F1/10 , G05B11/01 , G05F1/00
CPC分类号： H02M3/1584
摘要： In some embodiments, a multi-phase converter with dynamic phase adjustment is provided.
摘要翻译：在一些实施例中，提供了具有动态相位调整的多相转换器。

6. 发明授权

US08618788B2 Dynamically adjusted multi-phase regulator 有权
标题翻译：动态调节多相调节器
公开(公告)号：US08618788B2
公开(公告)日：2013-12-31
申请号：US11731161
申请日：2007-03-30
申请人： Malay Trivedi , Erik A. McShane , James T. Doyle
发明人： Malay Trivedi , Erik A. McShane , James T. Doyle
IPC分类号： G05F1/00
CPC分类号： H02M3/1584
摘要： In some embodiments, a multi-phase converter with dynamic phase adjustment is provided. In some embodiments, a controller may include circuitry to control how many phase legs are active based on output current and also which phase legs are to be enabled.
摘要翻译：在一些实施例中，提供了具有动态相位调整的多相转换器。在一些实施例中，控制器可以包括用于基于输出电流以及哪些相位腿被启用来控制多少相位线是有效的电路。

7. 发明授权

US07952160B2 Packaged voltage regulator and inductor array 有权
标题翻译：封装电压调节器和电感器阵列
公开(公告)号：US07952160B2
公开(公告)日：2011-05-31
申请号：US11968115
申请日：2007-12-31
申请人： Nicholas D. Triantafillou , Malay Trivedi , Erik A. McShane , James T. Doyle , Mark J. Kachmarek
发明人： Nicholas D. Triantafillou , Malay Trivedi , Erik A. McShane , James T. Doyle , Mark J. Kachmarek
IPC分类号： H01L21/70
CPC分类号： H01L23/645 , H01F2017/0086 , H01L2224/16227 , H01L2224/16265 , H01L2924/0002 , H01L2924/19103 , H01L2924/19104 , H01L2924/3011 , H01L2924/00
摘要： Inductors packaged with a voltage regulator for an integrated circuit within the same package are deposited to a sufficient thickness to reduce resistance and improve the quality factor. Furthermore, the voltage regulator switches currents through the inductors at a relatively high frequency such that the overall size and inductances of the inductors may be reduced. As a consequence, integrating both the integrated circuits including a voltage regulator and associated inductor array in a single package is facilitated. Other embodiments are described and claimed.
摘要翻译：与同一封装内的集成电路的电压调节器封装的电感器被沉积到足够的厚度以降低电阻并提高品质因数。此外，电压调节器以相对高的频率切换电流通过电感器，使得可以减小电感器的总体尺寸和电感。因此，将包括电压调节器和相关联的电感器阵列的集成电路集成在单个封装中是便利的。描述和要求保护其他实施例。

8. 发明申请

US20120117348A1 TECHNIQUES FOR SECURITY MANAGEMENT PROVISIONING AT A DATA STORAGE DEVICE 有权
标题翻译：用于在数据存储设备上提供安全管理的技术
公开(公告)号：US20120117348A1
公开(公告)日：2012-05-10
申请号：US12941915
申请日：2010-11-08
申请人： Nicholas D. Triantafillou , Paritosh Saxena , Robert W. Strong , Richard J. Heiler , Eliezer Tamir , Simoni Ben-Michael , Brad W. Stewart , Akshay R. Kadam , Men Long , James T. Doyle , Hormuzd M. Khosravi , Lokpraveen B. Mosur , Edward J. Pullin , Paul S. Schmitz , Carol L. Barrett , Paul J. Thadikaran
发明人： Nicholas D. Triantafillou , Paritosh Saxena , Robert W. Strong , Richard J. Heiler , Eliezer Tamir , Simoni Ben-Michael , Brad W. Stewart , Akshay R. Kadam , Men Long , James T. Doyle , Hormuzd M. Khosravi , Lokpraveen B. Mosur , Edward J. Pullin , Paul S. Schmitz , Carol L. Barrett , Paul J. Thadikaran
IPC分类号： G06F12/14
CPC分类号： G06F21/566
摘要： Techniques for a data storage device to locally implement security management functionality. In an embodiment, a security management process of the data storage device is to determine whether an access to non-volatile media of the data storage device is authorized. In certain embodiments, the data storage device is to restrict access to a secure region of the non-volatile storage media, the secure region to store information used and/or generated by a security management process of the data storage device.
摘要翻译：用于数据存储设备本地实现安全管理功能的技术。在一个实施例中，数据存储设备的安全管理过程是确定对数据存储设备的非易失性介质的访问是否被授权。在某些实施例中，数据存储设备将限制对非易失性存储介质的安全区域的访问，该安全区域用于存储由数据存储设备的安全管理过程使用和/或生成的信息。

9. 发明授权

US07498845B1 Power supply switching at circuit block level to reduce integrated circuit input leakage currents 有权
标题翻译：电源切换电路块级降低集成电路输入漏电流
公开(公告)号：US07498845B1
公开(公告)日：2009-03-03
申请号：US11880648
申请日：2007-07-23
申请人： James T. Doyle
发明人： James T. Doyle
IPC分类号： H03K19/096
CPC分类号： H03K19/00346 , H03K19/0941
摘要： Leakage currents at IC inputs can be avoided while the IC is disabled by providing a switch that is responsive to deactivation of an enable input to isolate functional circuitry of the IC from one of the power supply nodes of the IC. This eliminates power supply current while the IC is disabled. Further unwanted current flow can be avoided while the IC is disabled by providing a switch that is responsive to the enable input for selectively connecting and disconnecting the base of a reference voltage transistor to and from the transistor's grounded collector, which collector is defined by the substrate of the IC. Disconnection of the base from the grounded substrate/collector eliminates base current and thus prevents emitter-to-collector current flow through the transistor when the IC is disabled.
摘要翻译：可以通过提供响应于使能输入的去激活而将IC与IC的电源节点之一隔离的开关来禁用IC来禁止IC输入端的泄漏电流。这可以在IC禁用时消除电源电流。通过提供响应于使能输入的开关来禁用IC，可以避免IC的不需要的电流流动，该开关用于选择性地将参考电压晶体管的基极连接到晶体管的接地集电极和从晶体管的接地集电极断开，该集电极由衬底的IC。基极与接地的基板/集电极的断开消除了基极电流，因此当IC被禁用时，防止发射极到集电极电流流过晶体管。

10. 发明授权

US07493149B1 Method and system for minimizing power consumption in mobile devices using cooperative adaptive voltage and threshold scaling 有权
标题翻译：使用协作自适应电压和阈值缩放来最小化移动设备功耗的方法和系统
公开(公告)号：US07493149B1
公开(公告)日：2009-02-17
申请号：US10106428
申请日：2002-03-26
申请人： James T. Doyle , Dragan Maksimovic
发明人： James T. Doyle , Dragan Maksimovic
IPC分类号： H04M1/73
CPC分类号： G06F1/3203 , H04W52/0258 , Y02D70/142 , Y02D70/164
摘要： A method for minimizing power consumption in a mobile device using cooperative adaptive voltage and threshold scaling is provided that includes receiving a supply voltage, a PMOS back bias voltage, and an NMOS back bias voltage. A clock signal is received. The clock signal is propagated through a timing comparison circuit. An output of the timing comparison circuit is examined. A determination is made regarding whether to request more power based on the output of the timing comparison circuit. A voltage control signal is sent to request more power when a determination is made to request more power based on the output of the timing comparison circuit.
摘要翻译：提供一种使用协作自适应电压和阈值缩放来最小化移动设备中的功耗的方法，其包括接收电源电压，PMOS反向偏置电压和NMOS背置偏置电压。接收时钟信号。时钟信号通过定时比较电路传播。检查定时比较电路的输出。确定是否基于定时比较电路的输出请求更多的功率。当确定基于定时比较电路的输出请求更多功率时，发送电压控制信号以请求更多功率。

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