专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090020827A1 THIN GATE ELECTRODE CMOS DEVICES AND METHODS OF FABRICATING SAME 有权
标题翻译：薄门电极CMOS器件及其制造方法
公开(公告)号：US20090020827A1
公开(公告)日：2009-01-22
申请号：US11780519
申请日：2007-07-20
申请人： Jack A. Mandelman , William Robert Tonti
发明人： Jack A. Mandelman , William Robert Tonti
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L29/66545 , H01L21/28194 , H01L29/4958 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/6659
摘要： A CMOS device and method of forming the CMOS device. The device including a source and a drain formed in a semiconductor substrate, the source and the drain and separated by a channel region of the substrate; a gate dielectric formed on a top surface of the substrate and a very thin metal or metal alloy gate electrode formed on a top surface of the gate dielectric layer, a polysilicon line abutting and in electrical contact with the gate electrode, the polysilicon line thicker than the gate electrode. The method including, forming the gate electrode by forming a trench above the channel region and depositing metal into the trench.
摘要翻译：一种CMOS器件及其形成方法。所述器件包括形成在半导体衬底中的源极和漏极，所述源极和漏极由衬底的沟道区分隔开; 形成在基板的顶表面上的栅极电介质和形成在栅极电介质层的顶表面上的非常薄的金属或金属合金栅电极，与栅电极邻接并与之电接触的多晶硅线，多晶硅线比栅电极。该方法包括：通过在沟道区域上方形成沟槽并将金属沉积到沟槽中形成栅电极。

2. 发明授权

US07906390B2 Thin gate electrode CMOS devices and methods of fabricating same 有权
标题翻译：薄栅极CMOS器件及其制造方法
公开(公告)号：US07906390B2
公开(公告)日：2011-03-15
申请号：US11780519
申请日：2007-07-20
申请人： Jack A. Mandelman , William Robert Tonti
发明人： Jack A. Mandelman , William Robert Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L29/66545 , H01L21/28194 , H01L29/4958 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/6659
摘要： A CMOS device and method of forming the CMOS device. The device including a source and a drain formed in a semiconductor substrate, the source and the drain and separated by a channel region of the substrate; a gate dielectric formed on a top surface of the substrate and a very thin metal or metal alloy gate electrode formed on a top surface of the gate dielectric layer, a polysilicon line abutting and in electrical contact with the gate electrode, the polysilicon line thicker than the gate electrode. The method including, forming the gate electrode by forming a trench above the channel region and depositing metal into the trench.
摘要翻译：一种CMOS器件及其形成方法。所述器件包括形成在半导体衬底中的源极和漏极，所述源极和漏极由衬底的沟道区分隔开; 形成在基板的顶表面上的栅极电介质和形成在栅极电介质层的顶表面上的非常薄的金属或金属合金栅电极，与栅电极邻接并与之电接触的多晶硅线，多晶硅线比栅电极。该方法包括：通过在沟道区域上方形成沟槽并将金属沉积到沟槽中形成栅电极。

3. 发明申请

US20090001481A1 DIGITAL CIRCUITS HAVING ADDITIONAL CAPACITORS FOR ADDITIONAL STABILITY 审中-公开
标题翻译：具有附加电容器的数字电路用于额外的稳定性
公开(公告)号：US20090001481A1
公开(公告)日：2009-01-01
申请号：US11768270
申请日：2007-06-26
申请人： Ethan Harrison Cannon , Toshiharu Furukawa , David Vaclav Horak , Jack A. Mandelman , William Robert Tonti
发明人： Ethan Harrison Cannon , Toshiharu Furukawa , David Vaclav Horak , Jack A. Mandelman , William Robert Tonti
IPC分类号： H01L27/105 , H01L21/8238
CPC分类号： H01L27/0733 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L28/40
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a shallow trench isolation (STI) region on the semiconductor substrate, and (c) a first semiconductor transistor on the semiconductor substrate. The first semiconductor transistor includes (I) a first source/drain region, (ii) a second source/drain region, and (iii) a first gate electrode region. The first and second source/drain regions are doped with a same doping polarity. The semiconductor structure further includes a first doped region in the semiconductor substrate. The first doped region is on a first side wall and a bottom wall of the STI region. The first doped region is in direct physical contact with the second source/drain region. The first doped region and the second source/drain region are doped with a same doping polarity.
摘要翻译：半导体结构及其形成方法。半导体结构包括（a）半导体衬底，（b）半导体衬底上的浅沟槽隔离（STI）区域，以及（c）半导体衬底上的第一半导体晶体管。第一半导体晶体管包括（I）第一源极/漏极区域，（ii）第二源极/漏极区域，以及（iii）第一栅极电极区域。第一和第二源/漏区掺杂相同的掺杂极性。半导体结构还包括在半导体衬底中的第一掺杂区域。第一掺杂区域位于STI区域的第一侧壁和底壁上。第一掺杂区域与第二源极/漏极区域直接物理接触。第一掺杂区域和第二源极/漏极区域掺杂相同的掺杂极性。

4. 发明授权

US5937289A Providing dual work function doping 失效
标题翻译：提供双重功能掺杂
公开(公告)号：US5937289A
公开(公告)日：1999-08-10
申请号：US3106
申请日：1998-01-06
申请人： Gary Bela Bronner , Jeffrey P. Gambino , Jack A. Mandelman , Carl J. Radens , William Robert Tonti
发明人： Gary Bela Bronner , Jeffrey P. Gambino , Jack A. Mandelman , Carl J. Radens , William Robert Tonti
IPC分类号： H01L21/225 , H01L21/28 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L21/8238
CPC分类号： H01L21/28035 , H01L21/82345
摘要： Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.
摘要翻译：通过在第一导电类型的栅极结构的至少一个侧壁上掺杂选定数量的具有自对准绝缘层的栅极结构的结构，从而提供栅极结构的阵列，从而提供一些掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的导电类型。还提供了栅极结构的阵列，其中各个栅极结构在其顶部部分上包含自对准的绝缘层，并且其中一些栅极结构被掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的导电类型。

5. 发明授权

US08112729B2 Method and system for selective stress enablement in simulation modeling 有权
标题翻译：模拟建模中选择性应力启用的方法和系统
公开(公告)号：US08112729B2
公开(公告)日：2012-02-07
申请号：US12426342
申请日：2009-04-20
申请人： William Robert Tonti , Richard Quimby Williams
发明人： William Robert Tonti , Richard Quimby Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5009
摘要： A method and system for modeling an integrated circuit. The method includes converting a representation of the integrated circuit into design shapes of design levels of a design of the integrated circuit; adding control shapes to the design, the control shapes not defining any physical part of the integrated circuit; extracting layout-dependent stress parameters of the devices from the design levels of the design based on the control shapes and the design shapes; converting the layout-dependent stress parameters to stress parameters using a stress algorithm; generating stressed device parameters from the stress parameters using a compact model; and simulating performance of the integrated circuit using the stressed device parameters in a simulation model of the integrated circuit design.
摘要翻译：一种集成电路建模方法和系统。该方法包括将集成电路的表示转换为集成电路设计的设计级别的设计形状; 将控制形状添加到设计中，控制形状不限定集成电路的任何物理部分; 基于控制形状和设计形状，从设计的设计级别提取设备的布局相关应力参数; 使用应力算法将布局依赖应力参数转换为应力参数; 使用紧凑型模型从应力参数产生应力器件参数; 并在集成电路设计的仿真模型中使用应力器件参数来模拟集成电路的性能。

6. 发明授权

US07919347B2 Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes 有权
标题翻译：制造P-I-N二极管的方法，P-I-N二极管的结构和P-I-N二极管的设计结构
公开(公告)号：US07919347B2
公开(公告)日：2011-04-05
申请号：US12349018
申请日：2009-01-06
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens , William Robert Tonti
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens , William Robert Tonti
IPC分类号： H01L29/868
CPC分类号： H01L29/868 , H01L29/6609
摘要： Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer on surfaces of the trench; depositing a doped polysilicon layer to fill remaining space in the trench, performing a chemical mechanical polish so top surfaces of the intrinsic epitaxial silicon layer and the doped polysilicon layer are coplanar; forming a dielectric isolation layer in the substrate; forming a dielectric layer on top of the isolation layer; and forming a first metal contact to the doped polysilicon layer through the dielectric layer and a second contact to the doped region the dielectric and through the isolation layer.
摘要翻译：制造P-I-N二极管的方法，P-I-N二极管的结构和P-I-N二极管的设计结构。一种方法包括：在硅衬底中形成沟槽; 在所述衬底中形成邻接所述沟槽的掺杂区域; 在沟槽的表面上生长本征的外延硅层; 沉积掺杂多晶硅层以填充沟槽中的剩余空间，执行化学机械抛光，使得本征外延硅层和掺杂多晶硅层的顶表面是共面的; 在衬底中形成绝缘隔离层; 在隔离层的顶部形成介电层; 以及通过介电层形成第一金属接触到掺杂多晶硅层，以及通过第二接触到掺杂区域介电层并通过隔离层。

7. 发明授权

US07875960B2 Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates 失效
标题翻译：用于形成这种混合取向基板的混合取向基板和晶体压印方法
公开(公告)号：US07875960B2
公开(公告)日：2011-01-25
申请号：US12182560
申请日：2008-07-30
申请人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti
发明人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L29/04
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/045
摘要： A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.
摘要翻译：一种在硅衬底上具有绝缘层的半导体结构，通过绝缘层从衬底分离出的多个电隔离绝缘体上硅（SOI）区域，以及延伸穿过绝缘体的多个电隔离硅体区域层到基底。 SOI区域中的每一个以第一晶体取向取向，并且另外数量的SOI区域中的每一个以与第一晶体取向不同的第二晶体取向取向。体硅区域各自定向为具有第三晶体取向。还提供了形成SOI区域和体硅区域的镶嵌或印记方法。

8. 发明申请

US20100320563A1 ELECTRONIC FUSES IN SEMICONDUCTOR INTEGRATED CIRCUITS 有权
标题翻译：半导体集成电路中的电子熔丝
公开(公告)号：US20100320563A1
公开(公告)日：2010-12-23
申请号：US12870921
申请日：2010-08-30
申请人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti , Chih-Chao Yang
发明人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti , Chih-Chao Yang
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/76807 , H01L21/76892 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A structure. The structure includes: a substrate; a first electrode in the substrate; a dielectric layer on top of the substrate and the electrode; a second dielectric layer on the first dielectric layer, said second dielectric layer comprising a second dielectric material; a fuse element buried in the first dielectric layer, wherein the fuse element (i) physically separates, (ii) is in direct physical contact with both, and (iii) is sandwiched between a first region and a second region of the dielectric layer; and a second electrode on top of the fuse element, wherein the first electrode and the second electrode are electrically coupled to each other through the fuse element.
摘要翻译：一个结构。该结构包括：基底; 衬底中的第一电极; 在所述基板和所述电极的顶部上的介电层; 在所述第一介电层上的第二电介质层，所述第二电介质层包括第二电介质材料; 埋入第一介电层中的熔丝元件，其中熔融元件（i）物理分离，（ii）与二者直接物理接触，（iii）被夹在介电层的第一区域和第二区域之间; 以及在所述熔丝元件的顶部上的第二电极，其中所述第一电极和所述第二电极通过所述熔丝元件彼此电耦合。

9. 发明授权

US07737498B2 Enhanced stress-retention silicon-on-insulator devices and methods of fabricating enhanced stress retention silicon-on-insulator devices 失效
标题翻译：增强的应力保持硅绝缘体上的器件和制造增强的应力保持硅绝缘体上的器件的方法
公开(公告)号：US07737498B2
公开(公告)日：2010-06-15
申请号：US12116237
申请日：2008-05-07
申请人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed Hickory Rankin , Robert R. Robison , William Robert Tonti
发明人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed Hickory Rankin , Robert R. Robison , William Robert Tonti
IPC分类号： H01L21/00 , H01L21/338
CPC分类号： H01L29/78654 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/66772 , H01L29/7833 , H01L29/7848 , H01L29/7849 , H01L29/78603
摘要： Field effect transistor and methods of fabricating field effect transistors. The field effect transistors includes: a semiconductor substrate; a silicon oxide layer on the substrate; a stiffening layer on the silicon oxide layer; a single crystal silicon layer on the stiffening layer; a source and a drain on opposite sides of a channel region of the silicon layer; a gate electrode over the channel region and a gate dielectric between the gate electrode and the channel region.
摘要翻译：场效应晶体管和制造场效应晶体管的方法。场效应晶体管包括：半导体衬底; 衬底上的氧化硅层; 氧化硅层上的加强层; 加强层上的单晶硅层; 在硅层的沟道区的相对侧上的源极和漏极; 沟道区上的栅极电极和栅电极和沟道区之间的栅极电介质。

10. 发明授权

US07692250B2 Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures 有权
标题翻译：将镶嵌体FinFET和平面器件集成在共同衬底上的半导体结构以及用于形成这种半导体结构的方法
公开(公告)号：US07692250B2
公开(公告)日：2010-04-06
申请号：US11927110
申请日：2007-10-29
申请人： Roger Allen Booth, Jr. , Jack Allan Mandelman , William Robert Tonti
发明人： Roger Allen Booth, Jr. , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L27/12
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/82385 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.
摘要翻译：通过镶嵌法在公共衬底上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法以及通过该方法形成的半导体结构。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式