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1. 发明授权

US07784009B2 Electrically programmable π-shaped fuse structures and design process therefore 失效
标题翻译：因此电气可编程和形状的熔断器结构和设计过程
公开(公告)号：US07784009B2
公开(公告)日：2010-08-24
申请号：US11923833
申请日：2007-10-25
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
IPC分类号： G06F17/50
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuses for an integrated circuit and design structures thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void. The design structure for the fuse is embodied in a machine-readable medium for designing, manufacturing or testing a design of the fuse.
摘要翻译：提出了用于集成电路的电可编程保险丝及其设计结构，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和在第二支撑件上方的第二端子部分。保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个“形”结构。第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙之上。保险丝的设计结构体现在用于设计，制造或测试保险丝设计的机器可读介质中。

2. 发明授权

US07288804B2 Electrically programmable π-shaped fuse structures and methods of fabrication thereof 有权
标题翻译：电气可编程的pi形熔丝结构及其制造方法
公开(公告)号：US07288804B2
公开(公告)日：2007-10-30
申请号：US11372380
申请日：2006-03-09
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L27/10
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a α-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.
摘要翻译：提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和在第二支撑件上方的第二端子部分。保险丝，第一支撑件和第二支撑件在通过熔断元件的正面横截面中限定了α形结构。第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙上方，在一个实施例中，熔断元件由围绕熔丝元件的绝热介电材料覆盖。

3. 发明授权

US07656005B2 Electrically programmable π-shaped fuse structures and methods of fabrication thereof 失效
标题翻译：电气可编程的pi形熔丝结构及其制造方法
公开(公告)号：US07656005B2
公开(公告)日：2010-02-02
申请号：US11768254
申请日：2007-06-26
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.
摘要翻译：提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和在第二支撑件上方的第二端子部分。保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个pi形结构。第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙上方，在一个实施例中，熔断元件由围绕熔丝元件的绝热介电材料覆盖。

4. 发明授权

US07977766B2 Trench anti-fuse structures for a programmable integrated circuit 有权
标题翻译：用于可编程集成电路的沟槽反熔丝结构
公开(公告)号：US07977766B2
公开(公告)日：2011-07-12
申请号：US12537473
申请日：2009-08-07
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L21/00 , H01L23/535
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Trench anti-fuse structures, design structures embodied in a machine readable medium for designing, manufacturing, or testing a programmable integrated circuit. The anti-fuse structure includes a trench having a plurality of sidewalls that extend into a substrate, a doped region in the semiconductor material of the substrate proximate to the sidewalls of the trench, a conductive plug in the trench, and a dielectric layer on the sidewalls of the trench. The dielectric layer is disposed between the conductive plug and the doped region. The dielectric layer is configured so that a programming voltage applied between the doped region and the conductive plug causes a breakdown of the dielectric layer within a region of the trench. The trench sidewalls are arranged with a cross-sectional geometrical shape that is independent of position between a bottom wall of the deep trench and a top surface of the substrate.
摘要翻译：沟槽反熔丝结构，设计结构体现在用于设计，制造或测试可编程集成电路的机器可读介质中。反熔丝结构包括具有延伸到衬底中的多个侧壁的沟槽，靠近沟槽侧壁的衬底的半导体材料中的掺杂区域，沟槽中的导电插塞以及沟槽中的介电层沟槽的侧壁。电介质层设置在导电插塞和掺杂区域之间。电介质层被配置为使得施加在掺杂区域和导电插塞之间的编程电压导致沟槽区域内的电介质层的击穿。沟槽侧壁布置成具有与深沟槽的底壁和基板的顶表面之间的位置无关的横截面几何形状。

5. 发明授权

US07531388B2 Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabricating thereof 失效
标题翻译：具有窄宽度区域的电可编程熔丝结构被配置为增强电流拥挤及其制造方法
公开(公告)号：US07531388B2
公开(公告)日：2009-05-12
申请号：US11876942
申请日：2007-10-23
申请人： Roger A. Booth, Jr. , William R. Tonti , Jack A. Mandelman
发明人： Roger A. Booth, Jr. , William R. Tonti , Jack A. Mandelman
IPC分类号： H01L21/82 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.
摘要翻译：提出了电可编程熔丝结构及其制造方法，其中熔丝包括通过细长的熔丝元件互连的第一和第二端部。第一端子部分具有大于熔丝元件的最大宽度的最大宽度，并且熔丝包括第一端子部分和熔丝元件接合的变窄的宽度区域。狭窄宽度区域至少部分地延伸并包括第一端子部分的一部分。变窄区域中的第一端子部分的宽度小于第一端子部分的最大宽度，以增强其中的电流拥挤。在另一实施方式中，熔丝元件包括限制宽度区域，其中熔丝元件的宽度小于其最大宽度以增强其中的电流拥挤，并且受限宽度区域的长度小于熔丝元件的总长度。

6. 发明授权

US07417300B2 Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabrication thereof 有权
标题翻译：具有变宽的宽度区域的电可编程熔丝结构被配置为增强电流拥挤及其制造方法
公开(公告)号：US07417300B2
公开(公告)日：2008-08-26
申请号：US11372386
申请日：2006-03-09
申请人： Roger A. Booth, Jr. , Jack A. Mandelman , William R. Tonti
发明人： Roger A. Booth, Jr. , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.
摘要翻译：提出了电可编程熔丝结构及其制造方法，其中熔丝包括通过细长的熔丝元件互连的第一和第二端部。第一端子部分具有大于熔丝元件的最大宽度的最大宽度，并且熔丝包括第一端子部分和熔丝元件接合的变窄的宽度区域。狭窄宽度区域至少部分地延伸并包括第一端子部分的一部分。变窄区域中的第一端子部分的宽度小于第一端子部分的最大宽度，以增强其中的电流拥挤。在另一实施方式中，熔丝元件包括限制宽度区域，其中熔丝元件的宽度小于其最大宽度以增强其中的电流拥挤，并且受限宽度区域的长度小于熔丝元件的总长度。

7. 发明授权

US07550773B2 FinFET with top body contact 失效
标题翻译： FinFET与顶体接触
公开(公告)号：US07550773B2
公开(公告)日：2009-06-23
申请号：US11769032
申请日：2007-06-27
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7855
摘要： FinFETs are provided with a body contact on a top surface of a semiconductor fin. The top body contact may be self-aligned with respect to the semiconductor fin and the source and drain regions. Alternately, the source and drain regions may be formed recessed from the top surface of the semiconductor fin. The body or an extension of the body may be contacted above the channel or above one of the source and drain regions. Electrical shorts between the source and drain and the body contacts are avoided by the recessing of the source and drain regions from the top surface of the semiconductor fin.
摘要翻译： FinFET在半导体鳍片的顶表面上设有主体接触。顶部本体接触可以相对于半导体鳍片和源极和漏极区域自对准。或者，源极和漏极区域可以形成为从半导体鳍片的顶表面凹陷。主体或身体的延伸部可以在通道上方或者源极和漏极区域之上接触。通过源极和漏极区域从半导体鳍片的顶表面的凹陷来避免源极和漏极与主体接触之间的电短路。

8. 发明授权

US07700466B2 Tunneling effect transistor with self-aligned gate 有权
标题翻译：具有自对准栅极的隧道效应晶体管
公开(公告)号：US07700466B2
公开(公告)日：2010-04-20
申请号：US11828740
申请日：2007-07-26
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman
IPC分类号： H01L21/425 , H01L21/76 , H01L21/20 , H01L21/36 , H01L21/3205 , H01L21/4763 , H01L21/302 , H01L21/461
CPC分类号： H01L29/7391 , H01L23/485 , H01L29/66356 , Y10S438/926 , Y10S438/979
摘要： In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor.
摘要翻译：在一个实施例中，可以使用心轴和外部虚拟间隔件来形成第一导电类型区域。去除心轴以形成其中形成第二导电类型区域的凹陷区域。在另一个实施例中，心轴从浅沟槽隔离中移除以形成凹陷区域，其中形成内部虚拟间隔物。第一导电类型区域和第二导电区域形成在凹陷区域的其余部分内。进行退火，使得第一导电类型区域和第二导电类型区域通过扩散彼此邻接。栅电极形成为与第一和第二导电区域之间的p-n结自对准。由栅电极控制的可能是亚光刻的p-n结构成本发明的隧道效应晶体管。

9. 发明授权

US08652916B2 Self aligned impact-ionization MOS (I-MOS) device and methods of manufacture 失效
标题翻译：自对准冲击电离MOS（I-MOS）器件及其制造方法
公开(公告)号：US08652916B2
公开(公告)日：2014-02-18
申请号：US13426966
申请日：2012-03-22
申请人： Roger A. Booth, Jr. , Paul Chang , Kangguo Cheng , Chengwen Pei , William R. Tonti
发明人： Roger A. Booth, Jr. , Paul Chang , Kangguo Cheng , Chengwen Pei , William R. Tonti
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L29/66356 , H01L29/7391
摘要： A method of forming a semiconductor structure, including forming a gate structure on a substrate; performing a first angled implantation on a first side of the gate structure to form a first doped region in the substrate, the first doped region partially extends within a channel of the gate structure and the gate structure blocks the first angled implantation from affecting the substrate on a second side of the gate structure; forming sidewall spacers on sidewalls of the gate; and forming a second doped region in the substrate on the second side of the gate, spaced apart from the channel.
摘要翻译：一种形成半导体结构的方法，包括在衬底上形成栅极结构; 在所述栅极结构的第一侧上执行第一成角度的注入以在所述衬底中形成第一掺杂区域，所述第一掺杂区域在所述栅极结构的沟道内部分地延伸，并且所述栅极结构阻挡所述第一成角度注入以影响所述衬底门结构的第二面; 在所述浇口的侧壁上形成侧壁间隔物; 以及在所述栅极的所述衬底的第二侧上形成与所述沟道间隔开的第二掺杂区域。

10. 发明授权

US08691697B2 Self-aligned devices and methods of manufacture 失效
标题翻译：自对准装置和制造方法
公开(公告)号：US08691697B2
公开(公告)日：2014-04-08
申请号：US12943956
申请日：2010-11-11
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： H01L21/31056 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the another patterned line to the substrate.
摘要翻译：一种方法包括在具有预定间距的基底上形成图案线。该方法还包括在图案化线的侧壁上形成间隔壁。该方法还包括在相邻图案线的间隔壁侧壁之间的空间中形成材料。该方法还包括通过在相邻图案化线的间隔壁侧壁之间的空间中保护材料同时去除间隔壁侧壁而从该材料形成另一图案化线。该方法还包括将图案化线和另一图案化线的图案转移到衬底。

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