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    • 1. 发明申请
    • Configurable ping-pong buffers for USB buffer descriptor tables
    • 用于USB缓冲区描述符表的可配置乒乓缓冲区
    • US20060020721A1
    • 2006-01-26
    • US11075149
    • 2005-03-08
    • Igor WojewodaRoss FoslerRawin Rojvanit
    • Igor WojewodaRoss FoslerRawin Rojvanit
    • G06F3/06
    • G06F13/38
    • A digital device having selectable modes for USB communications buffer management in a USB interface of the digital device. These modes may comprise (1) no ping-pong buffer support, (2) ping-pong buffer support for some endpoints, e.g., support for OUT endpoint 0 only, and (3) ping-pong buffer support for all endpoints. In the no ping-pong buffer support mode, no hardware is required for automatic ping-pong buffer management. The Buffer Descriptor Tables may comprise a maximum of 128 memory locations, e.g., 16 IN endpoints and 16 OUT endpoints, each with at least one buffer descriptor, and each comprising four (4) memory locations. In the ping-pong buffer support for OUT endpoint 0 only mode, the buffer descriptor Tables may comprise a maximum of 132 memory locations, e.g., 16 OUT endpoints with an EVEN and an ODD endpoint 0, 16 IN endpoints, each with at least one descriptor, e.g., memory locations. This mode assures that endpoint 0 setup transfers may be serviced without delay while only requiring a minimal number of memory locations for the remainder of the buffer descriptors. In the ping-pong buffer support for all endpoints mode, automatic ping-pong buffer management may be provided for all endpoints. The Buffer Descriptor Tables may comprise a maximum of 256 memory locations, e.g., 16 IN endpoints and 16 OUT endpoints, an EVEN and ODD set for each, each with one descriptor, e.g., four (4) memory locations. This mode assures that all endpoint transfers may be serviced substantially without delay.
    • 一种数字设备,其具有用于在数字设备的USB接口中的USB通信缓冲器管理的可选模式。 这些模式可以包括(1)不支持乒乓缓冲器支持,(2)对于某些端点的乒乓缓冲器支持,例如仅支持OUT端点0,以及(3)对所有端点的乒乓缓冲器支持。 在无乒乓缓冲支持模式下,无需硬件自动乒乓缓冲区管理。 缓冲器描述符表可以包括最多128个存储器位置,例如16个IN端点和16个OUT端点,每个具有至少一个缓冲器描述符,并且每个包括四(4)个存储器位置。 在乒乓缓冲区支持OUT端点0的唯一模式下,缓冲区描述符表可以包含最多132个存储器位置,例如16个OUT端点,具有偶数和ODD端点0,16 IN端点,每个具有至少一个 描述符,例如内存位置。 该模式确保端点0建立传输可以无延迟地被服务,而仅需要缓冲器描述符的剩余部分的最小数量的存储器位置。 在所有端点模式的乒乓缓冲区支持中,可以为所有端点提供自动乒乓缓冲区管理。 缓冲器描述符表可以包括最多256个存储器位置,例如16个IN端点和16个OUT端点,为每个存储器单元设置一个EVEN和ODD,每个具有一个描述符,例如四(4)个存储器位置。 该模式确保所有端点传输可以在没有延迟的情况下实际进行维护。
    • 2. 发明申请
    • Method and apparatus for configuring a cyclic redundancy check (CRC) generation circuit to perform CRC on a data stream
    • 用于配置循环冗余校验(CRC)生成电路以对数据流执行CRC的方法和装置
    • US20070016842A1
    • 2007-01-18
    • US11180821
    • 2005-07-13
    • Roshan SamuelRawin Rojvanit
    • Roshan SamuelRawin Rojvanit
    • H03M13/00
    • H03M13/6516H03M13/09
    • A method and apparatus for configuring a cyclic redundancy check (CRC) generation circuit to perform CRC on a data stream are disclosed. The method includes storing a generator polynomial associated with a CRC equation in a register, where the generator polynomial has a length capable of varying such that the length has any value less than or equal to a number of bits associated with a CRC generation circuit. A bit position of the CRC generation circuit that corresponds to the length of the generator polynomial is selected by using a first multiplexer to generate a feedback value. The CRC generation circuit is programmed to calculate a CRC checksum based on the generator polynomial stored in the register and the feedback value from the selected bit position.
    • 公开了一种用于配置循环冗余校验(CRC)产生电路以对数据流执行CRC的方法和装置。 该方法包括将与CRC方程相关联的生成多项式存储在寄存器中,其中生成多项式具有能够变化的长度,使得长度具有小于或等于与CRC生成电路相关联的位数的任何值。 通过使用第一多路复用器来选择对应于生成多项式的长度的CRC生成电路的比特位置,以产生反馈值。 CRC生成电路被编程为基于存储在寄存器中的生成多项式和来自所选位位置的反馈值来计算CRC校验和。