专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2008053283A Manufacturing method for semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2008053283A
公开(公告)日：2008-03-06
申请号：JP2006225358
申请日：2006-08-22
申请人： Interuniversitair Micro Electronica Centrum Vzw , Matsushita Electric Ind Co Ltd , インターウニベルシテールマイクロエレクトロニカツェントラムフェーゼットウェー , 松下電器産業株式会社
发明人： YAMAMOTO KAZUHIKO
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/823842 , H01L21/28061 , H01L21/28088 , H01L21/823835
摘要： PROBLEM TO BE SOLVED: To obtain a manufacturing method for a semiconductor device capable of easily controlling the nitrogen composition of a gate electrode, in a MOSFET having the gate electrode composed of a metallic nitride film.
SOLUTION: The manufacturing method for the semiconductor device has a process (a) for forming an insulating film 15 on a semiconductor substrate 11, and a process (b) for forming a first conductive film 16 as the film consisting of a material, containing no nitrogen on the insulating film 15. The manufacturing method further has a process (c) for forming a second conductive film 18 as the film comprising the material containing nitrogen on the first conductive film 16, and a process (d) for forming the gate electrode by patterning the second conductive film 18 and the first conductive film 16, while forming a gate insulating film by patterning the insulating film 15.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：为了获得能够容易地控制栅电极的氮组成的半导体器件的制造方法，在具有由金属氮化物膜构成的栅电极的MOSFET中。解决方案：半导体器件的制造方法具有用于在半导体衬底11上形成绝缘膜15的工艺（a）和用于形成第一导电膜16作为由材料构成的膜的工艺（b）在绝缘膜15上不含氮的方法。制造方法还具有用于形成第二导电膜18的方法（c），所述第二导电膜18作为包含在第一导电膜16上含有氮的材料的膜，以及用于形成通过图案化第二导电膜18和第一导电膜16，同时通过图案化绝缘膜15形成栅极绝缘膜来形成栅极电极。（C）2008，JPO和INPIT

2. 发明专利

JP2008205012A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008205012A
公开(公告)日：2008-09-04
申请号：JP2007036440
申请日：2007-02-16
申请人： Interuniversitair Micro Electronica Centrum Vzw , Matsushita Electric Ind Co Ltd , インターウニベルシテールマイクロエレクトロニカツェントラムフェーゼットウェー , 松下電器産業株式会社
发明人： MIHASHI RIICHIRO , SINGANAMALLA RAGHU
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/82345 , H01L21/28088 , H01L21/823842 , H01L27/088 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that includes a gate insulating film ensuring high quality even if it is formed in a fine structure and assures higher reliability and high-speed operation.
SOLUTION: The semiconductor device includes a p-type MISFET including a p-type active region 1003 and an n-type active region 1004 formed within a semiconductor substrate 1001, a gate insulating film 1006 formed on the upper surface of the p-type active region 1003, and a first gate electrode including a first electrode forming film 1015 having the concentration of La at the upper part thereof higher than that of La at the other part. Moreover, the semiconductor device also includes an n-type MISFET including a gate insulating film 1006 formed on the upper surface of the n-type active region 1004 and a second gate electrode including a second electrode forming film 1014 having the concentration of Al at the upper part thereof higher than that of Al at the other part.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种包括栅极绝缘膜的半导体器件，其即使形成为精细结构也能确保高质量，并且确保更高的可靠性和高速度操作。解决方案：半导体器件包括p型MISFET，其包括形成在半导体衬底1001内的p型有源区1003和n型有源区1004，形成在p的上表面上的栅极绝缘膜1006 型有源区1003以及第一栅极，其包括第一电极形成膜1015，其第一电极形成膜1015的上部的La浓度高于另一部分的La。此外，半导体器件还包括n型MISFET，其包括形成在n型有源区域1004的上表面上的栅极绝缘膜1006和包括第二栅极电极的第二栅极电极，第二栅极电极在第其上部分高于Al的另一部分。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2008251955A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008251955A
公开(公告)日：2008-10-16
申请号：JP2007093284
申请日：2007-03-30
申请人： Interuniversitair Micro Electronica Centrum Vzw , Matsushita Electric Ind Co Ltd , インターウニベルシテールマイクロエレクトロニカツェントラムフェーゼットウェー , 松下電器産業株式会社
发明人： MIHASHI RIICHIRO , OIKAWA KOTA , BARRY OSULLIVAN , KUBICEK STEFAN
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L27/0922 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device including a metal gate electrode having a suitable work function, which is capable of high-speed operation with depletion suppressed, and a manufacturing method thereof.
SOLUTION: The semiconductor device includes: a p-type active region 1003 and an n-type active region 1004 which are formed in a semiconductor substrate 1001; a first MISFET including a first gate insulating film formed on the upper surface of the p-type active region 1003 and a first gate electrode formed on the first gate insulating film and including a first electrode formation film 1007 containing a metal element; and a second MISFET including a second gate insulating film formed on the upper surface of the n-type active region 1004 and a second gate electrode formed on the second gate insulating film and including a second electrode formation film 1010. The second electrode formation film 1010 contains the same metal element as the first electrode formation film 1007 and has an oxygen content higher than the first electrode formation film 1007.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种包括具有适合的功函数的金属栅电极的半导体器件，其能够高效率地进行耗尽抑制，及其制造方法。解决方案：半导体器件包括：形成在半导体衬底1001中的p型有源区1003和n型有源区1004; 第一MISFET，包括形成在p型有源区1003的上表面上的第一栅极绝缘膜和形成在第一栅极绝缘膜上的第一栅电极，并且包括含有金属元素的第一电极形成膜1007; 以及第二MISFET，其包括形成在n型有源区域1004的上表面上的第二栅极绝缘膜和形成在第二栅极绝缘膜上并包括第二电极形成膜1010的第二栅电极。第二电极形成膜1010 含有与第一电极形成膜1007相同的金属元素，并且具有高于第一电极形成膜1007的氧含量。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2007288096A Semiconductor device, and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007288096A
公开(公告)日：2007-11-01
申请号：JP2006116591
申请日：2006-04-20
申请人： Interuniversitair Micro Electronica Centrum Vzw , Matsushita Electric Ind Co Ltd , インターウニベルシテールマイクロエレクトロニカツェントラムフェーゼットウェー , 松下電器産業株式会社
发明人： YAMAMOTO KAZUHIKO , FUJIMOTO HIROMASA , KOTANI TAKAFUMI
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L21/823443 , H01L21/82345 , H01L21/823835 , H01L21/823842
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device wherein an n-channel MOS transistor of low leakage current and low threshold voltage and a p-channel MOS transistor are formed on one substrate.
SOLUTION: The semiconductor device comprises: a first conductive transistor 31 which is formed on a semiconductor substrate 11, and has a first gate insulating film 32 and a first gate electrode 33; and a second conductive transistor 41 having a second gate insulating film 42 and a second gate electrode 43. The first gate electrode 33 is a metal gate electrode having a metal film 14a, and the second gate electrode 43 is a full-silicified gate electrode comprising a silicide film 26b.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其中在一个衬底上形成低漏电流和低阈值电压的n沟道MOS晶体管和p沟道MOS晶体管。解决方案：半导体器件包括：第一导电晶体管31，其形成在半导体衬底11上，并具有第一栅极绝缘膜32和第一栅极电极33; 以及具有第二栅极绝缘膜42和第二栅电极43的第二导电晶体管41.第一栅电极33是具有金属膜14a的金属栅电极，第二栅电极43是全硅化栅电极，包括硅化物膜26b。版权所有（C）2008，JPO＆INPIT

5. 发明申请

US20130245606A1 HYDROGEL BASED OCCLUSION SYSTEMS 审中-公开
标题翻译：基于HYDROGEL的监督系统
公开(公告)号：US20130245606A1
公开(公告)日：2013-09-19
申请号：US13832069
申请日：2013-03-15
申请人： UNIVERSITY COLLEGE CORK, NATIONAL UNIVERSITY OF IRELAND, CORK , INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW , KATHOLIEKE UNVIVERSITEIT LEUVEN - KU LEUVEN RESEARCH & DEVELOPMENT , UNIVERSITEIT GENT , RAMOT AT TEL-AVIV UNIVERSITY, LTD. , TECHNISCHE UNIVERSITEIT DELFT
发明人： Frank Albert STAM , Nathan JACKSON , Peter DUBRUEL , Kehinde ADESANYA , Anika EMBRECHTS , Eduardo MENDES, JR. , Hurcules Pereira NEVES , Paul HERIJGERS , Peter VERBRUGGHE , Yosi SHACHAM , Leeya ENGEL , Viacheslav KRYLOV
IPC分类号： A61B17/12
CPC分类号： A61B17/12109 , A61B17/12122 , A61B17/12181 , A61B17/1219 , A61B90/361 , A61B2017/1205 , A61B2090/061
摘要： A hydrogel based occlusion system, a method for occluding vessels, appendages or aneurysms, and a method for hydrogel synthesis are disclosed. The hydrogel based occlusion system includes a hydrogel having a shrunken and a swollen state and a delivery tool configured to deliver the hydrogel to a target occlusion location. The hydrogel is configured to permanently occlude the target occlusion location in the swollen state. The hydrogel may be an electro-activated hydrogel (EAH) which could be electro-activated with a delivery system to control the degree of swelling/shrinking.
摘要翻译：公开了一种基于水凝胶的闭塞系统，闭塞血管，附属物或动脉瘤的方法以及水凝胶合成方法。基于水凝胶的闭塞系统包括具有收缩和膨胀状态的水凝胶和被配置为将水凝胶递送到目标闭塞位置的递送工具。水凝胶被配置为在肿胀状态下永久闭塞目标闭塞位置。水凝胶可以是电活化水凝胶（EAH），其可以用递送系统电活化以控制膨胀/收缩的程度。

6. 发明申请

WO2004025720A1 MANUFACTURING AN IC 审中-公开
标题翻译：制造IC
公开(公告)号：WO2004025720A1
公开(公告)日：2004-03-25
申请号：PCT/IB2003/003770
申请日：2003-08-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW , NGUYEN HOANG, Viet , DAAMEN, Roel
发明人： NGUYEN HOANG, Viet , DAAMEN, Roel
IPC分类号： H01L21/321
CPC分类号： H01L21/3212 , H01L21/7684
摘要： The method for manufacturing an integrated circuit according to the invention starts with providing a pre-fabricated integrated circuit (10) having a surface (11) coated with a dielectric material (12), a barrier layer (14) and a metal (15). The dielectric material (12), which is separated from the metal (15) by the barrier layer (14), has an opening (13), which is filled with the metal (15). Portions of the metal (15) outside the opening (13) are removed by a first chemical mechanical polishing step, which preferentially removes the metal (15) to locally expose the barrier layer (14). Portions of the locally exposed barrier layer (14) are removed by a second chemical mechanical polishing step, which preferentially removes the barrier layer (14). According to the invention, the first chemical mechanical polishing step is repeated after the second chemical mechanical polishing step has been carried out. The apparatus is able to perform the method. The computer program is able to control the method.
摘要翻译：根据本发明的集成电路的制造方法开始于提供具有涂覆有电介质材料（12），阻挡层（14）和金属（15）的表面（11）的预制集成电路（10）。通过阻挡层（14）与金属（15）分离的电介质材料（12）具有填充有金属（15）的开口（13）。通过第一化学机械抛光步骤去除开口（13）外部的金属（15）的部分，其优先移除金属（15）以局部暴露阻挡层（14）。通过第二化学机械抛光步骤去除局部暴露的阻挡层（14）的部分，其优先去除阻挡层（14）。根据本发明，在进行了第二化学机械抛光步骤之后，重复第一化学机械抛光步骤。该装置能够执行该方法。计算机程序能够控制方法。

7. 发明申请

WO1997015078A1 POLYMER STUD GRID ARRAY 审中-公开
标题翻译：聚合物螺柱GRID ARRAY
公开(公告)号：WO1997015078A1
公开(公告)日：1997-04-24
申请号：PCT/EP1996004407
申请日：1996-10-10
申请人： SIEMENS N.V. , INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW , DUMOULIN, Ann , HEERMAN, Marcel , ROGGEN, Jean , BEYNE, Eric , VAN HOOF, Rita
发明人： SIEMENS N.V. , INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW
IPC分类号： H01L23/13
CPC分类号： H01L23/13 , H01L23/4334 , H01L24/48 , H01L2224/48227 , H01L2924/00014 , H01L2924/12042 , H01L2924/14 , H01L2924/15157 , H01L2924/15311 , H01L2924/1532 , H01L2924/16195 , H01L2924/181 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399
摘要： To improve the removal of waste heat, a polymer stud grid array is proposed with the following elements: an injection-moulded three-dimensional substrate (S) made from an electrically insulating polymer; polymer studs (PS) arranged in one plane on the underside of the substrate (S) and formed during the injection moulding process; external connections formed on the polymer studs (PS) by an end surface suitable for soldering; strip conductors formed at least on the underside of the substrate (S) and connecting the external connections to internal connections; at least one heat-conducting element (WL) partially coated by the injection moulding process; and at least one chip or wiring element (VE) mounted on the heat-conducting element and with connections which have electrically conducting links with the internal connections. The novel structure is suitable for power components or power blocks in a polymer stud grid array package.
摘要翻译：为了实现热损失的改进的耗散，聚合物螺柱栅阵列提出，用注射成型，电绝缘聚合物的三维基板（S）; 在基板的下侧（S），其布置在注射模制聚合物螺柱（PS）和扁平共同模制; 在聚合物螺柱（PS）用可焊接的端部表面形成的外部端子; 至少在基板（S），其连接到内部连接的外部连接形成导体轨道的下侧上; 基板（S）的注射模制中的至少一个被部分地模制的导热体（WL）; 和布置成与至少一个所述导热体（WL）芯片或布线元件（VE）上，它的连接是导电地连接到内部连接。新的设计特别适合于在聚合物螺柱栅阵列封装的功率器件或功率模块。

8. 发明申请

WO2009140707A1 CROSS-DOMAIN SOC ARCHITECTURE FOR DEPENDABLE EMBEDDED APPLICATIONS 审中-公开
标题翻译：用于可扩展嵌入式应用的跨域SOC架构
公开(公告)号：WO2009140707A1
公开(公告)日：2009-11-26
申请号：PCT/AT2009/000207
申请日：2009-05-20
申请人： TECHNISCHE UNIVERSITÄT WIEN , INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW PARTY'S , EL SALLOUM, Christian , HUBER, Bernhard , KOPETZ, Hermann , OBERMAISSER, Roman , ZAFALON, Roberto , GHERMAN, Valentin , KRONLOEF, Klaus , WARIS, Heikki , LENORMAND, Eric , MILLET, Philippe , BORTH, Michael , COUVREUR, Chantal , SURI, Neeraj , CAMPOS, Sergio , OVASKA, Eila , TIENSYRJÄ, Kari , GOEDECKE, Michael , HUFELD, Knut , TAZARI, Mohammad-Reza , PEREZ BERDUD, Antonio , PEREZ CERROLAZA, Juan Martin
发明人： EL SALLOUM, Christian , HUBER, Bernhard , KOPETZ, Hermann , OBERMAISSER, Roman , ZAFALON, Roberto , GHERMAN, Valentin , KRONLOEF, Klaus , WARIS, Heikki , LENORMAND, Eric , MILLET, Philippe , BORTH, Michael , COUVREUR, Chantal , SURI, Neeraj , CAMPOS, Sergio , OVASKA, Eila , TIENSYRJÄ, Kari , GOEDECKE, Michael , HUFELD, Knut , TAZARI, Mohammad-Reza , PEREZ BERDUD, Antonio , PEREZ CERROLAZA, Juan Martin
IPC分类号： G06F15/78 , G06F11/07
CPC分类号： G06F11/3636 , G06F15/7825
摘要： A computer architecture for dependable distributed embedded systems is presented. This architecture consists of a plurality of computational units that are interconnected by a hierarchy of heterogeneous communication networks. At the lowest level, one or more functional units, at least one diagnostic unit and at least one security unit are allocated to a single MPSoC in order to support the dependable operation. These units interact via a deterministic network-on-chip. The unique integration of functionality, dependability and security concerns in a single deterministic SoC is an important innovative aspect of this new architecture.
摘要翻译：提出了可靠的分布式嵌入式系统的计算机架构。该架构由多个由异构通信网络层级相互连接的计算单元组成。在最低级别，为了支持可靠的操作，一个或多个功能单元，至少一个诊断单元和至少一个安全单元被分配给单个MPSoC。这些单元通过确定性的片上网络进行交互。功能，可靠性和安全性问题在单一确定性SoC中的独特集成是这一新架构的重要创新方面。

9. 发明申请

WO1997015077A1 POLYMER STUD-MATRIX HOUSING FOR MICROWAVE CIRCUIT ARRANGEMENTS 审中-公开
标题翻译：聚合物HÖCKERMATRIX住房微波电路
公开(公告)号：WO1997015077A1
公开(公告)日：1997-04-24
申请号：PCT/EP1996004404
申请日：1996-10-10
申请人： SIEMENS N.V. , INTERUNIVERSITAIR MICRO-ELECTRONICA-CENTRUM VZW , DUMOULIN, Ann , HEERMAN, Marcel , ROGGEN, Jean , BEYNE, Eric , VAN HOOF, Rita
发明人： SIEMENS N.V. , INTERUNIVERSITAIR MICRO-ELECTRONICA-CENTRUM VZW
IPC分类号： H01L23/13
CPC分类号： H01L23/66 , H01L23/13 , H01L24/48 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/00014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399
摘要： A polymer stud grid array for microwave circuit systems is proposed with the following elements: an injection-moulded three-dimensional substrate (S) made from an electrically insulating polymer; polymer studs (PS) arranged in one plane on the underside of the substrate (S) and formed during the injection moulding process; signal connections formed on several polymer studs (PS) by an end surface suitable for soldering; a potential connection (PA) formed on at least one polymer stud by an end surface suitable for soldering; strip conductors (SL) formed on the underside of the substrate (S) by a first structured metal layer (MS1), a dielectric layer (DE1) and a second structured metal layer (MS2), the first structured metal layer (MS1) having an electrically conducting connection to the potential connection (PA) and the second structured metal layer (MS2) of the strip conductors (SL) connecting the signal connections (SA) to dedicated internal connections (IA); and at least one microwave switching circuit (MIC) whose connections have electrically conducting connections with the internal connections (IA).
摘要翻译：它提出了一种用于微波电路装置的聚合物螺柱栅阵列，用注射模制，由电绝缘聚合物的，在基片（S）的下侧立体基板（S），其布置在注射模制聚合物螺柱（PS）平面和共同模制，在多个聚合物螺柱由第一结构化金属层上形成由可软焊端面（SA）在所述基板（S）形成的带状线（SL）的下侧形成，在至少一种聚合物螺柱（PS）用可焊接的端部表面（PA）形成电势端子，信号端子（PS）（MS1），介电层（DE1）和第二结构的金属层（MS2）被形成，其中所述第一结构化金属层（MS1）到电位连接（PA）导电地连接，并且其中，所述带状线的第二结构化金属层（MS2）（SL），所述信号连接（SA）具有相关联的附件的 nanschlüssen（IA）连接，并布置成与基片（S）上的至少一个，具有其端子连接到内部连接（IA）的微波集成电路（MIC）是导电连接。

10. 发明申请

WO1996009646A1 POLYMER STUD GRID ARRAY 审中-公开
标题翻译：聚合物螺柱GRID ARRAY
公开(公告)号：WO1996009646A1
公开(公告)日：1996-03-28
申请号：PCT/EP1995003763
申请日：1995-09-22
申请人： SIEMENS N.V. , INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW , HEERMAN, Marcel , WILLE, Joost , VAN PUYMBROECK, Jozef , ROGGEN, Jean , BEYNE, Eric , VAN HOOF, Rita
发明人： SIEMENS N.V. , INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW
IPC分类号： H01L23/13
CPC分类号： H01L24/81 , B29L2031/3493 , H01L23/13 , H01L23/49816 , H01L24/48 , H01L2224/1319 , H01L2224/16 , H01L2224/48091 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/3025 , H05K3/027 , H05K3/3431 , H05K3/4007 , H05K2201/0367 , H05K2201/09045 , H05K2201/09118 , H01L2224/45099 , H01L2924/00
摘要： The new structure comprises: an injection moulded three-dimensional substrate (S) made from an electrically insulating polymer; two-dimensionally configured polymer bumps (PS) formed during the injection-moulding process on the underside of the substrate (S); external connections (AA) formed on the polymer bumps (PS) by solderable end surfaces; conducting paths (LZ) at least on the underside of the substrate (S) to connect the external connections (AA) to inner connections (IA1); and at least one chip (C1) mounted on the substrate (S) with connections (CA1) which are electro-conductively linked to the inner connections. The novel structure, which is suitable for single-, few- or multi-chip modules, combines the advantages of a Ball Grid Array with those of MID ( M oulded I nterconnection D evices) technology, and the manufacture and metallization of the polymer bumps (PS) can be done within the framework of the process steps needed for MID technology and at minimal additional cost.
摘要翻译：新的设计包括一个注塑成型的，由电绝缘聚合物的，在基片（S）的表面的下侧立体基板（S），其布置和在注射成型共同模制的聚合物柱（PS），由可焊接的端部表面形成的聚合物柱（PS）的外部连接（ AA），至少在所述基板（S）形成的导体轨迹（LZ），它的外部连接（AA）连接到内部连接（IA1）和基板（S）上的至少一个的下侧排列的芯片（C1），其连接（CA1 ）电传导地连接到内部连接。新用于单，Few-芯片或多芯片模块的适当设计结合了MID技术（中号 oulded的优点的球栅阵列的优点我 nterconnection ð evices）。聚合物螺柱（PS）的制备和金属化然后可以作为与最小的额外努力无论如何在MID技术所需步骤的一部分来执行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式