专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20160197188A1 SEMICONDUCTOR DEVICE HAVING EMBEDDED STRAIN-INDUCING PATTERN AND METHOD OF FORMING THE SAME 有权
公开(公告)号：US20160197188A1
公开(公告)日：2016-07-07
申请号：US15071502
申请日：2016-03-16
申请人： Dong-Suk Shin , Myung-Sun Kim , Seong-Jin Nam , Pan-Kwi Park , Hoi-Sung Chung , Nae-In Lee
发明人： Dong-Suk Shin , Myung-Sun Kim , Seong-Jin Nam , Pan-Kwi Park , Hoi-Sung Chung , Nae-In Lee
IPC分类号： H01L29/78 , H01L29/51 , H01L27/11 , H01L29/45 , H01L27/088 , H01L29/08 , H01L29/165
CPC分类号： H01L27/1104 , H01L21/02532 , H01L21/02636 , H01L21/28247 , H01L21/30604 , H01L21/823807 , H01L21/823814 , H01L27/088 , H01L27/1116 , H01L29/0847 , H01L29/1083 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/513 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66575 , H01L29/6659 , H01L29/66636 , H01L29/7827 , H01L29/7833 , H01L29/7834 , H01L29/7845 , H01L29/7848 , H01L29/785 , H01L29/78696
摘要： In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

2. 发明申请

US20160079424A1 SEMICONDUCTOR DEVICES INCLUDING A STRESSOR IN A RECESS AND METHODS OF FORMING THE SAME 审中-公开
公开(公告)号：US20160079424A1
公开(公告)日：2016-03-17
申请号：US14951932
申请日：2015-11-25
申请人： Dong-Suk SHIN , Chul-Woong Lee , Hoi-Sung Chung , Young-Tak Kim , Nae-In Lee
发明人： Dong-Suk SHIN , Chul-Woong Lee , Hoi-Sung Chung , Young-Tak Kim , Nae-In Lee
IPC分类号： H01L29/78 , H01L29/08 , H01L29/165 , H01L29/66 , H01L29/167
CPC分类号： H01L29/7848 , H01L21/02636 , H01L21/30604 , H01L21/823412 , H01L21/823425 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L29/045 , H01L29/0603 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/66545 , H01L29/6656 , H01L29/66568 , H01L29/66575 , H01L29/66636 , H01L29/7833 , H01L29/7834
摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

3. 发明申请

US20160049512A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
公开(公告)号：US20160049512A1
公开(公告)日：2016-02-18
申请号：US14925679
申请日：2015-10-28
申请人： Dong Hyuk Kim , Dongsuk Shin , Myungsun Kim , Hoi Sung Chung
发明人： Dong Hyuk Kim , Dongsuk Shin , Myungsun Kim , Hoi Sung Chung
IPC分类号： H01L29/78 , H01L29/165 , H01L29/08 , H01L27/088 , H01L29/06
CPC分类号： H01L29/7848 , H01L21/02057 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/30608 , H01L21/3065 , H01L21/823412 , H01L21/823425 , H01L27/088 , H01L27/0924 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/66636
摘要： A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.

4. 发明授权

US08921192B2 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08921192B2
公开(公告)日：2014-12-30
申请号：US13615825
申请日：2012-09-14
申请人： Dong Hyuk Kim , Hoi Sung Chung , Myungsun Kim , Dongsuk Shin
发明人： Dong Hyuk Kim , Hoi Sung Chung , Myungsun Kim , Dongsuk Shin
IPC分类号： H01L21/336 , H01L29/66 , H01L21/02 , H01L29/78 , H01L29/165
CPC分类号： H01L29/7834 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L29/0692 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A MOS transistor includes a pair of impurity regions formed in a substrate as spaced apart from each other, and a gate electrode formed on a region of the substrate located between the pair of impurity regions. Each of the impurity regions is formed of a first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The first epitaxial layer is formed of at least one first sub-epitaxial layer and a respective second sub-epitaxial layer stacked on each first sub-epitaxial layer. An impurity concentration of the first sub-epitaxial layer is less than that of the second sub-epitaxial layer.
摘要翻译： MOS晶体管包括在彼此间隔开的基板中形成的一对杂质区，以及形成在位于该对杂质区之间的基板的区域上的栅电极。每个杂质区由第一外延层，第一外延层上的第二外延层和第二外延层上的第三外延层形成。第一外延层由堆叠在每个第一子外延层上的至少一个第一子外延层和相应的第二子外延层形成。第一子外延层的杂质浓度小于第二子外延层的杂质浓度。

5. 发明授权

US08637373B2 Transistors and methods of manufacturing the same 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US08637373B2
公开(公告)日：2014-01-28
申请号：US13410475
申请日：2012-03-02
申请人： Hoi-Sung Chung , Dong-Suk Shin , Dong-Hyuk Kim , Myung-Sun Kim
发明人： Hoi-Sung Chung , Dong-Suk Shin , Dong-Hyuk Kim , Myung-Sun Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/30608 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer.
摘要翻译：在制造晶体管的方法中，在包括硅的衬底上形成栅极结构。蚀刻与栅极结构相邻的衬底的上部，以在衬底中形成第一凹部。在第一凹部中形成包括硅 - 锗的初步的第一外延层。蚀刻初步第一外延层的上部以在初步第一外延层上形成第二凹槽。此外，蚀刻与第二凹槽相邻的初步第一外延层的一部分，从而将初步第一外延层转变为第一外延层。在位于第一外延层上的第二凹槽中形成包括硅 - 锗的第二外延层。

6. 发明申请

US20120241815A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120241815A1
公开(公告)日：2012-09-27
申请号：US13422077
申请日：2012-03-16
申请人： Dong Hyuk KIM , Dongsuk Shin , Myungsun Kim , Hoi Sung Chung
发明人： Dong Hyuk KIM , Dongsuk Shin , Myungsun Kim , Hoi Sung Chung
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/7848 , H01L21/02057 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/30608 , H01L21/3065 , H01L21/823412 , H01L21/823425 , H01L27/088 , H01L27/0924 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/66636
摘要： A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.
摘要翻译：制造一个或多个半导体器件的方法包括在半导体衬底中形成沟槽，执行循环过程以从沟槽去除污染物，以及在沟槽上形成外延层。循环过程包括将含有锗烷，氯化氢和氢的第一反应气体和含有氯化氢和氢的第二反应气体依次提供到半导体衬底上。

7. 发明申请

US20110241071A1 Semiconductor Devices Having Field Effect Transistors With Epitaxial Patterns in Recessed Regions 有权
标题翻译：具有场效应晶体管的半导体器件在嵌入区域中具有外延图案
公开(公告)号：US20110241071A1
公开(公告)日：2011-10-06
申请号：US13078159
申请日：2011-04-01
申请人： Dongsuk Shin , Dong Hyuk Kim , Myungsun Kim , YongJoo Lee , Hoi Sung Chung
发明人： Dongsuk Shin , Dong Hyuk Kim , Myungsun Kim , YongJoo Lee , Hoi Sung Chung
IPC分类号： H01L29/06
CPC分类号： H01L29/7834 , H01L29/6653 , H01L29/6659 , H01L29/66636
摘要： A semiconductor device includes a device isolation pattern, a gate line, and an epitaxial pattern. The device isolation pattern is disposed in a semiconductor substrate to define an active area. The gate line intersects the active area. The epitaxial pattern fills a recess region in the active area at one side of the gate line and includes a different constituent semiconductor element than the semiconductor substrate. The recess region includes a first inner sidewall that is adjacent to the device isolation pattern and extends in the lengthwise direction of the gate, and a second inner sidewall that extends in the direction perpendicular to the lengthwise direction of the gate line. The active area forms the first inner sidewall of the recess, while the device isolation layer forms at least a portion of the second inner sidewall of the recess. The epitaxial pattern contacts the first inner sidewall and the second inner sidewall of the recess region.
摘要翻译：半导体器件包括器件隔离图案，栅极线和外延图案。器件隔离图案设置在半导体衬底中以限定有源区。栅极线与有效区域相交。外延图案填充栅极线一侧的有源区域中的凹陷区域，并且包括与半导体衬底不同的构成半导体元件。所述凹部区域包括与所述器件隔离图案相邻并沿所述栅极的长度方向延伸的第一内侧壁和沿与所述栅极线的长度方向垂直的方向延伸的第二内侧壁。有源区域形成凹部的第一内侧壁，而器件隔离层形成凹部的第二内侧壁的至少一部分。外延图案接触凹陷区域的第一内侧壁和第二内侧壁。

8. 发明申请

US20100171181A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL SOURCE/DRAIN 审中-公开
标题翻译：形成具有外来源/排水的半导体器件的方法
公开(公告)号：US20100171181A1
公开(公告)日：2010-07-08
申请号：US12640944
申请日：2009-12-17
申请人： Hwa Sung Rhee , Myung Sun Kim , Ho Lee , Hoi Sung Chung
发明人： Hwa Sung Rhee , Myung Sun Kim , Ho Lee , Hoi Sung Chung
IPC分类号： H01L27/06 , H01L21/8238
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method of forming a semiconductor device includes forming a device isolation region in a silicon substrate to define an nMOS region and a pMOS region. A p-well is formed in the nMOS region and an n-well in the pMOS region. Gate structures are formed over the p-well and n-well, each gate structure including a stacked structure comprising a gate insulating layer and a gate electrode. A resist mask covers the nMOS region and exposes the pMOS region. Trenches are formed in the substrate on opposite sides of the gate structures of the pMOS region. SiGe layers are grown in the trenches of the pMOS region. The resist mask is removed from the nMOS region. Carbon is implanted to an implantation depth simultaneously on both the nMOS region and the pMOS region to form SiC on the nMOS region and SiGe on the pMOS region.
摘要翻译：形成半导体器件的方法包括在硅衬底中形成器件隔离区以限定nMOS区和pMOS区。在nMOS区域中形成p阱，在pMOS区域中形成n阱。栅极结构形成在p阱和n阱上，每个栅极结构包括包括栅极绝缘层和栅电极的堆叠结构。抗蚀剂掩模覆盖nMOS区域并暴露pMOS区域。沟槽形成在pMOS区域的栅极结构的相对侧上的衬底中。 SiGe层生长在pMOS区域的沟槽中。从nMOS区域去除抗蚀剂掩模。在nMOS区域和pMOS区域上同时植入碳到注入深度，以在nMOS区域上形成SiC，在pMOS区域上形成SiGe。

9. 发明申请

US20160218214A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
公开(公告)号：US20160218214A1
公开(公告)日：2016-07-28
申请号：US15092171
申请日：2016-04-06
申请人： Dong Hyuk Kim , Dongsuk Shin , Myungsun Kim , Hoi Sung Chung
发明人： Dong Hyuk Kim , Dongsuk Shin , Myungsun Kim , Hoi Sung Chung
IPC分类号： H01L29/78 , H01L29/16 , H01L27/092 , H01L29/165 , H01L29/06 , H01L29/08 , H01L29/161
CPC分类号： H01L29/7848 , H01L21/02057 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/30608 , H01L21/3065 , H01L21/823412 , H01L21/823425 , H01L27/088 , H01L27/0924 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/66636
摘要： A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.

10. 发明授权

US09397216B2 Semiconductor devices including a stressor in a recess and methods of forming the same 有权
标题翻译：包括凹部中的应力器的半导体器件及其形成方法
公开(公告)号：US09397216B2
公开(公告)日：2016-07-19
申请号：US14938172
申请日：2015-11-11
申请人： Dong-Suk Shin , Chul-Woong Lee , Hoi-Sung Chung , Young-Tak Kim , Nae-In Lee
发明人： Dong-Suk Shin , Chul-Woong Lee , Hoi-Sung Chung , Young-Tak Kim , Nae-In Lee
IPC分类号： H01L29/66 , H01L29/78 , H01L21/8234 , H01L21/8238 , H01L29/04 , H01L29/06 , H01L27/088 , H01L29/08 , H01L29/165 , H01L29/167
CPC分类号： H01L29/7848 , H01L21/02636 , H01L21/30604 , H01L21/823412 , H01L21/823425 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L29/045 , H01L29/0603 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/66545 , H01L29/6656 , H01L29/66568 , H01L29/66575 , H01L29/66636 , H01L29/7833 , H01L29/7834
摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.
摘要翻译：提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。所述方法可以包括在有源区中形成包含磷的快速蚀刻区域，并且通过使快速蚀刻区域凹陷来在有源区中形成第一沟槽。所述方法还可以包括通过使用定向蚀刻工艺扩大第一沟槽并在第二沟槽中形成应力源来在有源区域中形成第二沟槽。第二沟槽可以包括有源区的切口部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式