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1. 发明授权

US06519667B2 Bus control system 失效
公开(公告)号：US06519667B2
公开(公告)日：2003-02-11
申请号：US09991925
申请日：2001-11-26
申请人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
发明人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
IPC分类号： G06F1300
CPC分类号： G06F13/4027 , G06F13/36
摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

2. 发明授权

US06504529B1 Information processor input device thereof and display device 失效
标题翻译：信息处理器输入装置和显示装置
公开(公告)号：US06504529B1
公开(公告)日：2003-01-07
申请号：US09179870
申请日：1998-10-28
申请人： Yukihide Inagaki , Hideki Kamimaki , Tsuyoshi Nakagawa , Koichi Kimura , Hideaki Gemma
发明人： Yukihide Inagaki , Hideki Kamimaki , Tsuyoshi Nakagawa , Koichi Kimura , Hideaki Gemma
IPC分类号： G09G500
CPC分类号： G06F3/038 , G06F1/1616 , G06F1/1656 , G06F1/1669 , G06F1/1681 , G06F1/203 , G06F3/0231
摘要： An information processor including a keyboard, a main body and a display device. The keyboard is provided with plural infrared-ray emission elements which are located at different positions so as to face in different directions, and an identifying code setting switch for setting the identification code of the keyboard into an infrared-ray signal transmitted from each infrared-ray emission element. The main body includes plural infrared-ray receiving elements which are located at different positions so as to face in different directions, an identifying code setting switch for setting the identification code of the keyboard, and a keyboard controller for judging whether the same identification code as set by the identification code setting switch is contained in the infrared-ray signal which is received by any one of the infrared-ray receiving elements.
摘要翻译：一种包括键盘，主体和显示装置的信息处理器。键盘设置有位于不同位置的多个红外线发射元件，以便朝向不同的方向，以及识别码设置开关，用于将键盘的识别码设置为从每个红外线发射的红外线信号，射线发射元件。主体包括位于不同位置的多个红外线接收元件，以便朝向不同的方向，用于设置键盘的识别码的识别码设置开关，以及用于判断是否将相同的识别码与由识别码设定开关设定的红外线信号包含在由红外线接收元件中的任一个接收的红外线信号中。

3. 发明授权

US5774679A Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement 失效
公开(公告)号：US5774679A
公开(公告)日：1998-06-30
申请号：US774614
申请日：1996-12-30
申请人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
发明人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
IPC分类号： G06F13/362 , G06F13/00 , G06F13/12 , G06F13/364 , G06F13/38 , G06F13/42 , G06F13/14
CPC分类号： G06F13/364
摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.

4. 发明授权

US4879550A Method and system for loop communication 失效
标题翻译：循环通信的方法和系统
公开(公告)号：US4879550A
公开(公告)日：1989-11-07
申请号：US871995
申请日：1986-06-09
申请人： Yusuke Hino , Tohru Horimoto , Hideaki Gemma , Toshiharu Iwata , Kimitoshi Yamada
发明人： Yusuke Hino , Tohru Horimoto , Hideaki Gemma , Toshiharu Iwata , Kimitoshi Yamada
IPC分类号： H04M7/00 , H04L12/42 , H04L12/46
CPC分类号： H04L12/4625 , H04L12/4637
摘要： A composite loop communication network formed by combining a plurality of loop communication paths each provided with terminals with one another through a plurality of loop coupling devices so as to form a loop, is disclosed in which one of the terminals of each loop communication path is used as a management terminal, the management terminal of a loop communication path sets routing information on the communication between the loop communication path and a loop communication path adjacent thereto in a loop coupling device, and the loop coupling device selectively takes in data flowing through the former loop communication path, on the basis of the above routing information, to send the data from the loop coupling device to the latter loop communication path, thereby making possible the communication between terminals of different loop communication paths.
摘要翻译：公开了通过组合多个环路通信路径而形成的复合环通信网络，每个环路通信路径通过多个环路耦合设备彼此设置以形成环路，其中使用每个环路通信路径的一个终端作为管理终端，环路通信路径的管理终端在环路连接装置中设置环路通信路径与其相邻的环路通信路径之间的通信的路由信息，并且环路耦合设备选择性地接收流经前者的数据基于上述路由信息的环路通信路径将数据从环路耦合设备发送到后一环路通信路径，从而使不同环路通信路径的终端之间的通信成为可能。

5. 发明申请

US20070106832A1 Bus control system 失效
公开(公告)号：US20070106832A1
公开(公告)日：2007-05-10
申请号：US11642511
申请日：2006-12-21
申请人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
发明人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , G06F13/36
摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

6. 发明授权

US06606243B2 Information processing unit and information processing related units 有权
公开(公告)号：US06606243B2
公开(公告)日：2003-08-12
申请号：US09788529
申请日：2001-02-21
申请人： Hideki Kamimaki , Yukihide Inagaki , Tsuyoshi Nakagawa , Koichi Kimura , Hideaki Gemma , Hitoshi Kawaguchi
发明人： Hideki Kamimaki , Yukihide Inagaki , Tsuyoshi Nakagawa , Koichi Kimura , Hideaki Gemma , Hitoshi Kawaguchi
IPC分类号： G06F116
CPC分类号： G06F1/1616 , E05B73/0005 , E05B73/0082 , G06F1/1632 , G06F1/1635 , G06F1/1656 , G06F1/266
摘要： A labor of disconnecting many cables is omitted even when carrying a file basestation with an external storage loaded together with a main body. An information processing unit comprises: a main body having a CPU, a keyboard and a display unit; a file basestation with an external storage, such as an FD·D or a CD-ROM·D, loaded; and a portreplicator with many connectors loaded. Removal of the main body alone from the portreplicator or removal of the main body and the file basestation can omit the labor of disconnecting many cables connected to the portreplicator.

7. 发明授权

US5657458A Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment 失效
标题翻译：用于控制总线进行传送周期而不插入确认周期的方法
公开(公告)号：US5657458A
公开(公告)日：1997-08-12
申请号：US480397
申请日：1995-06-07
申请人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
发明人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
IPC分类号： G06F13/362 , G06F13/00 , G06F13/12 , G06F13/364 , G06F13/38 , G06F13/42
CPC分类号： G06F13/364
摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.
摘要翻译：一种信息处理系统，其中作为执行对模块的读取访问以作为从机操作的主机的模块请求总线仲裁器以提供具有总线主控请求信号的总线主控性，并且同时断言最后一个周期信号，以通知总线仲裁器下一个周期将是主机使用的最后一个周期的事实。随后，当主机已经使用由总线仲裁器通过总线使用授权信号授予的总线时，它通过在下一个周期中使用总线将地址传送到从机，从而开始读取访问。读取权限后，主人释放总线主控权。只有当从站未能接受传送的地址时，它会在地址的传输周期不被接受的两个周期之后重新生成重试请求信号。在这种情况下，在断言信号的周期之前执行传送两个周期的模块再次执行之前执行的传送。因此，要传输的地址只能在一个周期内传输到模块准备好接受地址。

8. 发明授权

US5604874A Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment 失效
公开(公告)号：US5604874A
公开(公告)日：1997-02-18
申请号：US480395
申请日：1995-06-07
申请人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
发明人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
IPC分类号： G06F13/362 , G06F13/00 , G06F13/12 , G06F13/364 , G06F13/38 , G06F13/42 , G06F15/16
CPC分类号： G06F13/364
摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.

9. 发明授权

US4638428A Polling control method and system 失效
标题翻译：轮询控制方法和系统
公开(公告)号：US4638428A
公开(公告)日：1987-01-20
申请号：US681028
申请日：1984-12-13
申请人： Hideaki Gemma , Masafumi Hino
发明人： Hideaki Gemma , Masafumi Hino
IPC分类号： G06F13/22
CPC分类号： G06F13/22
摘要： In a terminal control unit having a polling function to a plurality of terminal devices, the number of times of continuous non-response to the polling is counted for each terminal device address. If the number of times exceeds a predetermined number, a frequency of polling to that terminal device is lowered to eliminate unnecessary polling.
摘要翻译：在具有对多个终端设备的轮询功能的终端控制单元中，针对每个终端设备地址计数对轮询的连续不响应的次数。如果次数超过预定数量，则降低对该终端装置的轮询频率，以消除不必要的轮询。

10. 发明授权

US07177970B2 Bus control system 失效
标题翻译：总线控制系统
公开(公告)号：US07177970B2
公开(公告)日：2007-02-13
申请号：US10274881
申请日：2002-10-22
申请人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
发明人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
IPC分类号： G06F13/14 , G06F13/36
CPC分类号： G06F13/4027 , G06F13/36
摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.
摘要翻译：在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

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