专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07029991B2 Method for making a SOI semiconductor substrate with thin active semiconductor layer 有权
标题翻译：制造具有薄的有源半导体层的SOI半导体衬底的方法
公开(公告)号：US07029991B2
公开(公告)日：2006-04-18
申请号：US10312024
申请日：2001-06-21
申请人： Vincent Le Goascoz , Herve Jaouen
发明人： Vincent Le Goascoz , Herve Jaouen
IPC分类号： H01L21/322
CPC分类号： H01L21/26533 , H01L21/76243
摘要： The invention concerns a method comprising: 1) a first phase including steps which consist in forming in the upper part of a first initial semiconductor substrate a first layer of insulating material above a sectional plane of said first substrate, contacting the first layer of insulating material with the insulating upper part of a second initial substrate, so as to form a single layer of insulating material, a break at the sectional plane, so as to obtain an intermediate semiconductor substrate on the single insulating material layer; then, 2) in a second phase which consists in forming in the intermediate semiconductor substrate an additional insulating material layer adjacent to the single insulating material and topped with an upper layer of a final semiconductor substrate.
摘要翻译：本发明涉及一种方法，包括：1）包括以下步骤的第一相：第一阶段，其包括在第一初始半导体衬底的上部形成在所述第一衬底的截面上方的第一绝缘材料层，与第一绝缘材料层接触与第二初始衬底的绝缘上部形成单层绝缘材料，在截面上形成断裂，以在单个绝缘材料层上获得中间半导体衬底; 那么2）在第二阶段中，其包括在中间半导体衬底中形成与单个绝缘材料相邻的附加的绝缘材料层并且顶上最后的半导体衬底的上层。

2. 发明申请

US20060001113A1 Magnetic sensor of very high sensitivity 有权
标题翻译：磁传感器灵敏度非常高
公开(公告)号：US20060001113A1
公开(公告)日：2006-01-05
申请号：US11214248
申请日：2005-08-29
申请人： Herve Jaouen , Thomas Skotnicki , Malgorzata Jurczak
发明人： Herve Jaouen , Thomas Skotnicki , Malgorzata Jurczak
IPC分类号： H01L27/14 , H01L21/00
CPC分类号： G10K9/13 , G01D5/242 , G01L9/0042 , Y10T428/1157 , Y10T428/1171 , Y10T428/19
摘要： A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.
摘要翻译：磁传感器包括由导电材料制成的薄的可变形膜，该导电材料形成电容器的第一板，其导通电流。电容器的第二电容器板包括半导体衬底的掺杂区域。气体介质层分离两个板。由于由位于膜的平面中的磁场产生的洛伦兹力的作用并且垂直于通过其传导的电流线，膜变形。此外，还提供了用于制造该磁传感器的工艺以及使用该磁传感器来测量磁场的装置。

3. 发明授权

US06897545B2 Lateral operation bipolar transistor and a corresponding fabrication process 有权
标题翻译：横向操作双极晶体管和相应的制造工艺
公开(公告)号：US06897545B2
公开(公告)日：2005-05-24
申请号：US10142249
申请日：2002-05-09
申请人： Olivier Menut , Herve Jaouen
发明人： Olivier Menut , Herve Jaouen
IPC分类号： H01L29/06 , H01L29/10 , H01L27/102
CPC分类号： H01L29/1012 , H01L29/0649 , H01L29/735
摘要： The transistor includes an emitter region 17 disposed in a first isolating well 11, 150 formed in a semiconductor bulk. An extrinsic collector region 16 is disposed in a second isolating well 3, 150 formed in the semiconductor bulk SB and separated laterally from the first well by a bulk separator area 20. An intrinsic collector region is situated in the bulk separator area 20 in contact with the extrinsic collector region. An intrinsic base region 100 is formed which is thinner laterally than vertically and in contact with the intrinsic collector region and in contact with the emitter region through bearing on a vertical flank of the first isolating well facing a vertical flank of the second isolating well. An extrinsic base region 60 is formed which is substantially perpendicular to the intrinsic base region in the top part of the bulk separator area, and contact terminals C, B, E respectively in contact with the extrinsic collector region, the extrinsic base region, and the emitter region.
摘要翻译：晶体管包括设置在半导体本体中形成的第一隔离阱11,150中的发射极区17。外部集电极区域16设置在形成于半导体本体SB中的第二隔离阱3,150中，并且通过体分离器区域20与第一阱横向分离。内部集电极区域位于与外部集电极区域接触的体分离器区域20中。形成本征基区100，其横向比垂直地更薄并且与本征收集区相接触，并且通过轴承在第一隔离井的垂直侧面与第二隔离井的垂直侧面的垂直侧面接触。形成基本上垂直于本体分离器区域的顶部中的本征基极区域的外部基极区域60，以及分别与外部基极区域，外部基极区域和外部基极区域接触的接触端子C，B，E 发射区。

4. 发明授权

US06623993B2 Method of determining the time for polishing the surface of an integrated circuit wafer 有权
公开(公告)号：US06623993B2
公开(公告)日：2003-09-23
申请号：US09898523
申请日：2001-07-03
申请人： Emmanuel Perrin , Herve Jaouen
发明人： Emmanuel Perrin , Herve Jaouen
IPC分类号： G01R3126
CPC分类号： B24B37/013 , B24B37/042 , B24B49/03 , B24B49/16 , H01L21/31053
摘要： A method of determining the time for polishing the surface of an integrated circuit wafer on a polishing machine. A sample wafer is fabricated to include at least one high plateau and at least one low plateau joined by a sudden transition. At least one initial profile is topographically scanned, and the surface of the sample wafer is polished at a particular polishing pressure for a particular polishing time. The final profile of the polished layer is topographically scanned in the corresponding area, and the initial and final topographical scans of the sample wafer are converted into Fourier series. The surface of the wafer to be polished is topographically scanned, and the topographic scan of the wafer to be polished is converted into a Fourier series. The time for polishing the wafer to be polished is calculated from the Fourier series and the average thickness to be removed.

5. 发明授权

US6100595A Semiconductor device having optoelectronic remote signal-exchange means 失效
标题翻译：具有光电远程信号交换装置的半导体装置
公开(公告)号：US6100595A
公开(公告)日：2000-08-08
申请号：US105735
申请日：1998-06-26
申请人： Herve Jaouen , Michel Marty
发明人： Herve Jaouen , Michel Marty
IPC分类号： H01L33/00 , G02B6/42 , H01L27/14 , H01L31/0232 , H01L23/14 , G02B6/30
CPC分类号： G02B6/4212 , G02B6/4248 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204
摘要： A semiconductor device includes a chip forming an integrated circuit; a connection substrate; an internal coupling mechanism; and at least one optical communication system. The connection substrate comprises an external coupling mechanism for electrically coupling to a device other than the chip. The internal coupling mechanism electrically couples the integrated circuit to the external coupling mechanism. The at least one optical communication system comprises two optoelectronic parts. The first optoelectronic part is either an emitter or a receiver which is integrated into the chip and constitutes one component of the integrated circuit. The second optoelectronic part is borne by the connection substrate and is able to be externally connected to the connection substrate. The second optoelectronic part faces the first optoelectronic part and is capable of exchanging light signals with the first optoelectronic part.
摘要翻译：半导体器件包括形成集成电路的芯片; 连接基板; 内联机构; 和至少一个光通信系统。连接基板包括用于电耦合到除了芯片之外的装置的外部耦合机构。内部耦合机构将集成电路电耦合到外部耦合机构。所述至少一个光通信系统包括两个光电子部件。第一个光电子部分是集成到芯片中的发射极或接收器，并构成集成电路的一个部件。第二光电子部分由连接基板承载，并且能够从外部连接到连接基板。第二光电子部分面向第一光电子部分，并且能够与第一光电子部分交换光信号。

6. 发明授权

US06673703B2 Method of fabricating an integrated circuit 有权
标题翻译：制造集成电路的方法和具有单晶硅衬底的集成电路
公开(公告)号：US06673703B2
公开(公告)日：2004-01-06
申请号：US10171102
申请日：2002-06-13
申请人： Olivier Menut , Herve Jaouen
发明人： Olivier Menut , Herve Jaouen
IPC分类号： H01L21265
CPC分类号： H01L29/66272
摘要： A method of fabricating an integrated circuit including a monocrystalline silicon substrate, a layer of polycrystalline silicon on the top surface of the substrate and doped with at least two dopants with different rates of diffusion, in which method annealing is performed at a temperature and for a time such that a first dopant diffuses into a first zone and a second dopant diffuses into a second zone larger than the first zone.
摘要翻译：一种制造集成电路的方法，该集成电路包括单晶硅衬底，在该衬底的顶表面上的多晶硅层，并且掺杂有至少两种具有不同扩散速率的掺杂剂，其中在温度和时间，使得第一掺杂剂扩散到第一区域中，并且第二掺杂剂扩散到大于第一区域的第二区域中。

7. 发明申请

US20060258066A1 Electrically stabilized integrated circuit 审中-公开
标题翻译：电子稳压集成电路
公开(公告)号：US20060258066A1
公开(公告)日：2006-11-16
申请号：US11407849
申请日：2006-04-20
申请人： Jean-Pierre Schoellkopf , Philippe Roche , Herve Jaouen
发明人： Jean-Pierre Schoellkopf , Philippe Roche , Herve Jaouen
IPC分类号： H01L21/84
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1104
摘要： An integrated electronic circuit comprises active components disposed on the surface of a substrate and connected by electrical connections disposed within a metallization level. A dielectric material situated between the surface of the substrate and the metallization level, or in the metallization level, has a locally higher value of dielectric permittivity so as to selectively increase a capacitance between certain portions of the active components or of the connections. An electrical state of the circuit in operation is then stabilized, thanks to a higher electrical charge carried by the portions of the active components or of the connections whose capacitance is enhanced. The circuit can be a static random access memory cell.
摘要翻译：集成电子电路包括设置在基板的表面上并通过设置在金属化层级内的电连接而连接的有源元件。位于基板的表面和金属化水平或金属化水平之间的电介质材料具有局部较高的介电常数值，以便有选择地增加有源部件或连接的某些部分之间的电容。由于有源部件的部分或其电容增加的连接部分承载的电荷较高，所以运行中的电路的电气状态稳定。电路可以是静态随机存取存储单元。

8. 发明授权

US06423996B1 Process for fabricating a metal-metal capacitor within an integrated circuit, and corresponding integrated circuit 有权
标题翻译：在集成电路内制造金属 - 金属电容器的工艺及相应的集成电路
公开(公告)号：US06423996B1
公开(公告)日：2002-07-23
申请号：US09658221
申请日：2000-09-08
申请人： Michel Marty , Herve Jaouen
发明人： Michel Marty , Herve Jaouen
IPC分类号： H01L27108
CPC分类号： H01L28/40
摘要： A process for fabricating a metal-metal capacitor within an integrated circuit comprises the steps of: producing a first metal electrode, a second metal electrode, and a dielectric layer on top of a lower insulating layer; and depositing an upper insulating layer on top of the two metal electrodes and the dielectric layer. The integrated circuit comprises the insulating layer, a first metal layer which is on top of the lower insulating layer, and the upper insulating layer which is on top of the first metal layer. The capacitor comprises the first metal electrode, the second metal electrode, and the dielectric layer wherein each of the two metal electrodes is in contact with one side of the dielectric layer. The electrodes and the dielectric layer lie between the lower insulating layer, which supports a level of metallization (M1), and the upper insulating layer which covers this level of metallization.
摘要翻译：一种用于在集成电路内制造金属 - 金属电容器的工艺包括以下步骤：在下绝缘层的顶部上产生第一金属电极，第二金属电极和电介质层; 以及在所述两个金属电极和所述电介质层的顶部上沉积上绝缘层。集成电路包括绝缘层，位于下绝缘层顶部的第一金属层和位于第一金属层顶部的上绝缘层。电容器包括第一金属电极，第二金属电极和电介质层，其中两个金属电极中的每一个与电介质层的一侧接触。电极和电介质层位于支撑金属化水平（M1）的下绝缘层和覆盖这种金属化水平的上绝缘层之间。

9. 发明授权

US6081030A Semiconductor device having separated exchange means 失效
标题翻译：具有分离的交换装置的半导体装置
公开(公告)号：US6081030A
公开(公告)日：2000-06-27
申请号：US105355
申请日：1998-06-26
申请人： Herve Jaouen , Michel Marty
发明人： Herve Jaouen , Michel Marty
IPC分类号： H01L23/12 , H01F17/00 , H01L23/64 , H01L25/00 , H01L23/34
CPC分类号： H01L23/48 , H01L23/645 , H01L24/73 , H01F17/0006 , H01L2224/16225 , H01L2924/01004 , H01L2924/01033 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15174 , H01L2924/15311 , H01L2924/16195 , H01L2924/19103 , H01L2924/19104 , H01L2924/30107
摘要： A semiconductor device having separated exchange mechanism comprises a chip forming an integrated circuit; a connection substrate; device connection points or balls; and at least one exchange mechanism. The connection substrate comprises an external connection mechanism. The device connection points or balls are distributed in the form of a matrix and are located between the juxtaposed faces of the chip and of the connection substrate. The device connection points are connected to the external connection mechanism. The exchange mechanism comprises two parts. The two parts are arranged so as to be separated from each other and capable of exchanging signals between each other, in one or both directions. The first part is physically coupled to the chip. The second part is physically coupled to the connection substrate and is connected to the external connection mechanism.
摘要翻译：具有分离的交换机构的半导体器件包括形成集成电路的芯片; 连接基板; 设备连接点或球; 和至少一个交换机制。连接基板包括外部连接机构。设备连接点或球以矩阵的形式分布并且位于芯片的并置面和连接衬底之间。设备连接点连接到外部连接机构。交换机制包括两部分。这两个部分被布置成彼此分离并且能够在一个或两个方向上彼此之间交换信号。第一部分物理耦合到芯片。第二部分物理耦合到连接基板并连接到外部连接机构。

10. 发明授权

US06503812B2 Fabrication process for a semiconductor device with an isolated zone 有权
标题翻译：具有隔离区域的半导体器件的制造工艺
公开(公告)号：US06503812B2
公开(公告)日：2003-01-07
申请号：US10044829
申请日：2002-01-11
申请人： Olivier Menut , Guillaume Bouche , Herve Jaouen
发明人： Olivier Menut , Guillaume Bouche , Herve Jaouen
IPC分类号： H01L2176
CPC分类号： H01L21/76264 , H01L21/76283
摘要： The semiconductor device comprises a semiconductor substrate (SB) having locally at least one zone (ZL) terminating in the surface of the substrate and entirely bordered, along its lateral edges and its bottom, by an insulating material so as to be completely isolated from the rest of the substrate. The horizontal isolating layer may be a layer of constant thickness or a crenellated layer.
摘要翻译：半导体器件包括半导体衬底（SB），其具有局部至少一个区域（ZL），该区域（ZL）终止于衬底的表面，并且沿着其侧边缘及其底部通过绝缘材料整齐地界定，从而与绝缘材料完全隔离底物的剩余部分。水平隔离层可以是恒定厚度的层或钝化层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式