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    • 1. 发明授权
    • Insulated gate semiconductor device and method of manufacture
    • 绝缘栅半导体器件及其制造方法
    • US5817561A
    • 1998-10-06
    • US720509
    • 1996-09-30
    • Heemyong ParkVida IlderemAndreas A. Wild
    • Heemyong ParkVida IlderemAndreas A. Wild
    • H01L21/28H01L21/336H01L29/08H01L29/423H01L29/78H01L21/3205
    • H01L29/66659H01L21/28114H01L21/2815H01L29/0847H01L29/42376H01L29/7835
    • An insulated gate semiconductor device (10) has a double spacer gate structure (45). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate oxide (23) is then formed over the major surface (12) adjacent the sidewalls (22). A first polysilicon layer (24) is deposited on the gate oxide (23) and the stack. The first polysilicon layer (24) is etched to form a first conductive spacer (32) of the gate structure (45). A second polysilicon layer (44) is deposited on first spacer (32) and the stack. The second polysilicon layer (44) is then etched to form a second conductive spacer (46) of the gate structure (45). Because the double spacer gate structure (45) is formed without relying on photolithographic techniques, its size is smaller than the size of a gate structure formed using conventional photolithography.
    • 绝缘栅半导体器件(10)具有双间隔栅极结构(45)。 为了形成栅极结构(45),在半导体衬底(11)的主表面(12)上形成具有侧壁(22)的叠层。 然后在邻近侧壁(22)的主表面(12)上形成栅极氧化物(23)。 第一多晶硅层(24)沉积在栅极氧化物(23)和堆叠上。 蚀刻第一多晶硅层(24)以形成栅极结构(45)的第一导电间隔物(32)。 第二多晶硅层(44)沉积在第一间隔物(32)和堆叠体上。 然后蚀刻第二多晶硅层(44)以形成栅极结构(45)的第二导电间隔物(46)。 由于双重间隔栅极结构(45)不依赖于光刻技术而形成,因此其尺寸小于使用常规光刻形成的栅极结构的尺寸。
    • 2. 发明授权
    • Insulated gate semiconductor device
    • 绝缘栅半导体器件
    • US06097060A
    • 2000-08-01
    • US99807
    • 1998-06-18
    • Heemyong ParkVida IlderemAndreas A. Wild
    • Heemyong ParkVida IlderemAndreas A. Wild
    • H01L21/28H01L21/336H01L29/08H01L29/423H01L29/78H01L27/088H01L29/49
    • H01L29/66659H01L21/28114H01L21/2815H01L29/0847H01L29/42376H01L29/7835
    • An insulated gate semiconductor device (10) has a double spacer gate structure (45). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate oxide (23) is then formed over the major surface (12) adjacent the sidewalls (22). A first polysilicon layer (24) is deposited on the gate oxide (23) and the stack. The first polysilicon layer (24) is etched to form a first conductive spacer (32) of the gate structure (45). A second polysilicon layer (44) is deposited on first spacer (32) and the stack. The second polysilicon layer (44) is then etched to form a second conductive spacer (46) of the gate structure (45). Because the double spacer gate structure (45) is formed without relying on photolithographic techniques, its size is smaller than the size of a gate structure formed using conventional photolithography.
    • 绝缘栅半导体器件(10)具有双间隔栅极结构(45)。 为了形成栅极结构(45),在半导体衬底(11)的主表面(12)上形成具有侧壁(22)的叠层。 然后在邻近侧壁(22)的主表面(12)上形成栅极氧化物(23)。 第一多晶硅层(24)沉积在栅极氧化物(23)和堆叠上。 蚀刻第一多晶硅层(24)以形成栅极结构(45)的第一导电间隔物(32)。 第二多晶硅层(44)沉积在第一间隔物(32)和堆叠体上。 然后蚀刻第二多晶硅层(44)以形成栅极结构(45)的第二导电间隔物(46)。 由于双重间隔栅极结构(45)不依赖于光刻技术而形成,因此其尺寸小于使用常规光刻形成的栅极结构的尺寸。