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1. 发明授权

US5817561A Insulated gate semiconductor device and method of manufacture 失效
标题翻译：绝缘栅半导体器件及其制造方法
公开(公告)号：US5817561A
公开(公告)日：1998-10-06
申请号：US720509
申请日：1996-09-30
申请人： Heemyong Park , Vida Ilderem , Andreas A. Wild
发明人： Heemyong Park , Vida Ilderem , Andreas A. Wild
IPC分类号： H01L21/28 , H01L21/336 , H01L29/08 , H01L29/423 , H01L29/78 , H01L21/3205
CPC分类号： H01L29/66659 , H01L21/28114 , H01L21/2815 , H01L29/0847 , H01L29/42376 , H01L29/7835
摘要： An insulated gate semiconductor device (10) has a double spacer gate structure (45). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate oxide (23) is then formed over the major surface (12) adjacent the sidewalls (22). A first polysilicon layer (24) is deposited on the gate oxide (23) and the stack. The first polysilicon layer (24) is etched to form a first conductive spacer (32) of the gate structure (45). A second polysilicon layer (44) is deposited on first spacer (32) and the stack. The second polysilicon layer (44) is then etched to form a second conductive spacer (46) of the gate structure (45). Because the double spacer gate structure (45) is formed without relying on photolithographic techniques, its size is smaller than the size of a gate structure formed using conventional photolithography.
摘要翻译：绝缘栅半导体器件（10）具有双间隔栅极结构（45）。为了形成栅极结构（45），在半导体衬底（11）的主表面（12）上形成具有侧壁（22）的叠层。然后在邻近侧壁（22）的主表面（12）上形成栅极氧化物（23）。第一多晶硅层（24）沉积在栅极氧化物（23）和堆叠上。蚀刻第一多晶硅层（24）以形成栅极结构（45）的第一导电间隔物（32）。第二多晶硅层（44）沉积在第一间隔物（32）和堆叠体上。然后蚀刻第二多晶硅层（44）以形成栅极结构（45）的第二导电间隔物（46）。由于双重间隔栅极结构（45）不依赖于光刻技术而形成，因此其尺寸小于使用常规光刻形成的栅极结构的尺寸。

2. 发明授权

US06097060A Insulated gate semiconductor device 失效
标题翻译：绝缘栅半导体器件
公开(公告)号：US06097060A
公开(公告)日：2000-08-01
申请号：US99807
申请日：1998-06-18
申请人： Heemyong Park , Vida Ilderem , Andreas A. Wild
发明人： Heemyong Park , Vida Ilderem , Andreas A. Wild
IPC分类号： H01L21/28 , H01L21/336 , H01L29/08 , H01L29/423 , H01L29/78 , H01L27/088 , H01L29/49
CPC分类号： H01L29/66659 , H01L21/28114 , H01L21/2815 , H01L29/0847 , H01L29/42376 , H01L29/7835
摘要： An insulated gate semiconductor device (10) has a double spacer gate structure (45). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate oxide (23) is then formed over the major surface (12) adjacent the sidewalls (22). A first polysilicon layer (24) is deposited on the gate oxide (23) and the stack. The first polysilicon layer (24) is etched to form a first conductive spacer (32) of the gate structure (45). A second polysilicon layer (44) is deposited on first spacer (32) and the stack. The second polysilicon layer (44) is then etched to form a second conductive spacer (46) of the gate structure (45). Because the double spacer gate structure (45) is formed without relying on photolithographic techniques, its size is smaller than the size of a gate structure formed using conventional photolithography.
摘要翻译：绝缘栅半导体器件（10）具有双间隔栅极结构（45）。为了形成栅极结构（45），在半导体衬底（11）的主表面（12）上形成具有侧壁（22）的叠层。然后在邻近侧壁（22）的主表面（12）上形成栅极氧化物（23）。第一多晶硅层（24）沉积在栅极氧化物（23）和堆叠上。蚀刻第一多晶硅层（24）以形成栅极结构（45）的第一导电间隔物（32）。第二多晶硅层（44）沉积在第一间隔物（32）和堆叠体上。然后蚀刻第二多晶硅层（44）以形成栅极结构（45）的第二导电间隔物（46）。由于双重间隔栅极结构（45）不依赖于光刻技术而形成，因此其尺寸小于使用常规光刻形成的栅极结构的尺寸。

3. 发明授权

US06033231A Semiconductor device having a pedestal and method of forming 失效
标题翻译：具有基座的半导体器件和成形方法
公开(公告)号：US06033231A
公开(公告)日：2000-03-07
申请号：US121812
申请日：1998-07-24
申请人： Robert B. Davies , Andreas A. Wild , Diann M. Dow , Peter J. Zdebel , E. James Prendergast
发明人： Robert B. Davies , Andreas A. Wild , Diann M. Dow , Peter J. Zdebel , E. James Prendergast
IPC分类号： H01L21/336 , H01L21/762 , H01L21/8234 , H01L29/10 , H01L29/417 , H01L29/423 , H01L21/8238
CPC分类号： H01L29/41725 , H01L21/762 , H01L21/823412 , H01L29/1083 , H01L29/1087 , H01L29/66621 , H01L29/78 , H01L29/66537
摘要： A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60,97) that can be used to transport electrical signals across the device (10).
摘要翻译：梯形通道半导体器件（10）形成在基座（12）中。与传统的装置结构相比，底座（12）形成在基板（11）上并改善了装置（10）的电气特性。基座（12）具有由第一介电层（24）邻接以提供电隔离的侧面（13）。互连结构（90）可以可选地与装置（10）的形成一起形成。互连结构（90）具有多个导体（60,97），其可用于传输跨越设备（10）的电信号。

4. 发明授权

US5920102A Semiconductor device having a decoupling capacitor and method of making 失效
标题翻译：具有去耦电容器的半导体器件及其制造方法
公开(公告)号：US5920102A
公开(公告)日：1999-07-06
申请号：US867663
申请日：1997-05-30
申请人： Robert B. Davies , Andreas A. Wild , Peter J. Zdebel
发明人： Robert B. Davies , Andreas A. Wild , Peter J. Zdebel
IPC分类号： H01L27/06 , H01L29/76 , H01L29/94
CPC分类号： H01L27/0629
摘要： A semiconductor device (10) is formed in a pedestal structure (16) overlying an epitaxial layer (12) and a semiconductor substrate (11). The semiconductor device (10) includes a doped region (13) that forms a PN junction with the epitaxial layer (12). The semiconductor device (10) also includes a dielectric layer (22) that has an opening (23) that exposes a portion of the doped region (13) and an opening (24) that exposes a portion of the epitaxial layer (12). The openings (23, 24) are filled with a conductive material (36, 37) to provide contacts (100, 101). Due to the presence of the PN junction, the contacts (100, 101) are capacitively coupled to each other.
摘要翻译：半导体器件（10）形成在覆盖外延层（12）和半导体衬底（11）的基座结构（16）中。半导体器件（10）包括与外延层（12）形成PN结的掺杂区域（13）。半导体器件（10）还包括具有露出掺杂区域（13）的一部分的开口（23）和露出外延层（12）的一部分的开口（24）的电介质层（22）。开口（23,24）填充有导电材料（36,37）以提供触点（100,101）。由于PN结的存在，触点（100,101）彼此电容耦合。

5. 发明授权

US5818098A Semiconductor device having a pedestal 失效
标题翻译：具有基座的半导体器件
公开(公告)号：US5818098A
公开(公告)日：1998-10-06
申请号：US608864
申请日：1996-02-29
申请人： Robert B. Davies , Andreas A. Wild , Diann M. Dow , Peter J. Zdebel , E. James Prendergast
发明人： Robert B. Davies , Andreas A. Wild , Diann M. Dow , Peter J. Zdebel , E. James Prendergast
IPC分类号： H01L21/336 , H01L21/762 , H01L21/8234 , H01L29/10 , H01L29/417 , H01L29/423 , H01L23/58
CPC分类号： H01L29/41725 , H01L21/762 , H01L21/823412 , H01L29/1083 , H01L29/1087 , H01L29/66621 , H01L29/78 , H01L29/66537
摘要： A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60, 97) that can be used to transport electrical signals across the device (10).
摘要翻译：梯形通道半导体器件（10）形成在基座（12）中。与传统的装置结构相比，底座（12）形成在基板（11）上并改善了装置（10）的电气特性。基座（12）具有由第一介电层（24）邻接以提供电隔离的侧面（13）。互连结构（90）可以可选地与装置（10）的形成一起形成。互连结构（90）具有多个导体（60,97），可用于传输电信号跨过装置（10）。

6. 发明授权

US6051456A Semiconductor component and method of manufacture 失效
标题翻译：半导体元件及制造方法
公开(公告)号：US6051456A
公开(公告)日：2000-04-18
申请号：US216990
申请日：1998-12-21
申请人： Robert B. Davies , Andreas A. Wild
发明人： Robert B. Davies , Andreas A. Wild
IPC分类号： H01L21/331 , H01L21/336 , H01L21/8222 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L27/092 , H01L29/732 , H01L29/78 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/0623 , H01L21/8249
摘要： A semiconductor component includes an asymmetric transistor having two lightly doped drain regions (1300, 1701), a channel region (1702), a source region (1916) located within the channel region (1702), a drain region located outside the channel region (1702), a dielectric structure (1404) located over at least one of the two lightly doped drain regions (1300, 1701), two gate electrodes (1902, 1903) located at opposite sides of the dielectric structure (1404), a drain electrode (1901) overlying the drain region (1915), and a source electrode (1904) overlying the source region (1916). The semiconductor component also includes another transistor having an emitter electrode (122) located between a base electrode (121) and a collector electrode (123) where the base electrode (121) is formed over a dielectric structure (1405).
摘要翻译：半导体部件包括具有两个轻掺杂漏极区域（1300,1701），沟道区域（1702），位于沟道区域（1702）内的源极区域（1916））的不对称晶体管，位于沟道区域外部的漏极区域 1702），位于两个轻掺杂漏极区（1300,1701）中的至少一个上的电介质结构（1404），位于电介质结构（1404）的相对侧的两个栅电极（1902,1903），漏电极（1901）和覆盖源区（1916）的源电极（1904）。该半导体元件还包括另一晶体管，其具有位于介电结构（1405）之间形成基极（121）的基极（121）和集电极（123）之间的发射极（122）。

7. 发明授权

US5892379A Transistor protection circuit and method 失效
标题翻译：晶体管保护电路及方法
公开(公告)号：US5892379A
公开(公告)日：1999-04-06
申请号：US867661
申请日：1997-06-02
申请人： Juan Buxo , Andreas A. Wild , Gary H. Loechelt , Thomas E. Zirkle , E. James Prendergast , Patrice M. Parris
发明人： Juan Buxo , Andreas A. Wild , Gary H. Loechelt , Thomas E. Zirkle , E. James Prendergast , Patrice M. Parris
IPC分类号： H03K17/0812 , H03K19/003 , H03B1/00 , H03K17/687
CPC分类号： H03K17/08122 , H03K19/00315
摘要： A circuit and method protect a transistor (68, 70) from damage when controlling an input signal (V.sub.PROG) that exceeds a gate to channel stress voltage of the transistor. A small, low current protection transistor (64, 66) is serially coupled to the gate electrode of the transistor being protected. The gate of the protection transistor is biased to a voltage (V.sub.P, V.sub.N) of lower magnitude than the input signal to limit the voltage applied to the gate of the protected transistor to a value within the stress voltage of the protected transistor.
摘要翻译：当控制超过晶体管的栅极至沟道应力电压的输入信号（VPROG）时，电路和方法保护晶体管（68,70）免受损坏。一个小的低电流保护晶体管（64,66）串联耦合到被保护的晶体管的栅电极。保护晶体管的栅极被偏置为比输入信号更低的电压（VP，VN），以将施加到受保护晶体管的栅极的电压限制在受保护晶体管的应力电压内的值。

8. 发明授权

US5808362A Interconnect structure and method of forming 失效
标题翻译：互连结构和成型方法
公开(公告)号：US5808362A
公开(公告)日：1998-09-15
申请号：US609251
申请日：1996-02-29
申请人： Robert B. Davies , Andreas A. Wild , Peter J. Zdebel
发明人： Robert B. Davies , Andreas A. Wild , Peter J. Zdebel
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/06 , H01L29/10 , H01L29/417 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/41775 , H01L21/8234 , H01L29/0653 , H01L29/1083 , H01L29/1087 , H01L29/41783 , H01L29/66621 , H01L29/665 , H01L29/66537
摘要： A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60,97) that can be used to transport electrical signals across the device (10).
摘要翻译：梯形通道半导体器件（10）形成在基座（12）中。与传统的装置结构相比，底座（12）形成在基板（11）上并改善了装置（10）的电气特性。基座（12）具有由第一介电层（24）邻接以提供电隔离的侧面（13）。互连结构（90）可以可选地与装置（10）的形成一起形成。互连结构（90）具有多个导体（60,97），其可用于传输跨越设备（10）的电信号。

9. 发明授权

US5612244A Insulated gate semiconductor device having a cavity under a portion of a gate structure and method of manufacture 失效
标题翻译：绝缘栅半导体器件具有在栅极结构的一部分下方的空腔和制造方法
公开(公告)号：US5612244A
公开(公告)日：1997-03-18
申请号：US408657
申请日：1995-03-21
申请人： Robert B. Davies , Andreas A. Wild
发明人： Robert B. Davies , Andreas A. Wild
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/423 , H01L21/265 , H01L21/70 , H01L27/00
CPC分类号： H01L29/42368 , H01L21/823807 , H01L21/823828 , H01L29/66659 , H01L21/28167
摘要： An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor substrate (11). A gate oxide layer (26) is formed on the dopant well (13) wherein the gate oxide layer (26) and a gate structure (41) having a gate contact portion (43) and a gate extension portion (44). The gate contact portion (43) permits electrical contact to the gate structure (41), whereas the gate extension portion (44) serves as the active gate portion. A portion of the gate oxide (26) adjacent the gate contact portion (43) is thickened to lower a gate to drain capacitance of the field effect transistor (10) and thereby increase a bandwidth of the insulated gate field effect transistor (10).
摘要翻译：具有减小的栅极 - 漏极电容的绝缘栅场效应晶体管（10）和制造场效应晶体管（10）的方法。掺杂剂阱（13）形成在半导体衬底（11）中。栅极氧化物层（26）形成在掺杂剂阱（13）上，其中栅极氧化物层（26）和具有栅极接触部分（43）和栅极延伸部分（44）的栅极结构（41）。栅极接触部分（43）允许与栅极结构（41）的电接触，而栅极延伸部分（44）用作有源栅极部分。与栅极接触部分（43）相邻的栅极氧化物（26）的一部分被加厚以降低场效应晶体管（10）的栅极到漏极电容，从而增加绝缘栅极场效应晶体管（10）的带宽。

10. 发明授权

US6153905A Semiconductor component including MOSFET with asymmetric gate electrode where the drain electrode over portions of the lightly doped diffusion region without a gate dielectric 有权
标题翻译：半导体元件包括具有非对称栅极电极的MOSFET，其中漏电极在轻掺杂扩散区的部分上而没有栅极电介质
公开(公告)号：US6153905A
公开(公告)日：2000-11-28
申请号：US502694
申请日：2000-02-11
申请人： Robert B. Davies , Andreas A. Wild
发明人： Robert B. Davies , Andreas A. Wild
IPC分类号： H01L21/331 , H01L21/336 , H01L21/8222 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L27/092 , H01L29/732 , H01L29/78 , H01L29/788
CPC分类号： H01L27/0623 , H01L21/8249
摘要： A semiconductor component includes an asymmetric transistor having two lightly doped drain regions (1300, 1701), a channel region (1702), a source region (1916) located within the channel region (1702), a drain region located outside the channel region (1702), a dielectric structure (1404) located over at least one of the two lightly doped drain regions (1300, 1701), two gate electrodes (1902, 1903) located at opposite sides of the dielectric structure (1404), a drain electrode (1901) overlying the drain region (1915), and a source electrode (1904) overlying the source region (1916). The semiconductor component also includes another transistor having an emitter electrode (122) located between a base electrode (121) and a collector electrode (123) where the base electrode (121) is formed over a dielectric structure (1405).
摘要翻译：半导体部件包括具有两个轻掺杂漏极区域（1300,1701），沟道区域（1702），位于沟道区域（1702）内的源极区域（1916））的不对称晶体管，位于沟道区域外部的漏极区域 1702），位于两个轻掺杂漏极区（1300,1701）中的至少一个上的电介质结构（1404），位于电介质结构（1404）的相对侧的两个栅电极（1902,1903），漏电极（1901）和覆盖源区（1916）的源电极（1904）。该半导体元件还包括另一晶体管，其具有位于介电结构（1405）之间形成基极（121）的基极（121）和集电极（123）之间的发射极（122）。

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