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1. 发明申请

US20120115265A1 DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US20120115265A1
公开(公告)日：2012-05-10
申请号：US13354618
申请日：2012-01-20
申请人： Han-Tu LIN , Chien-Hung Chen , Shiun-Chang Jan
发明人： Han-Tu LIN , Chien-Hung Chen , Shiun-Chang Jan
IPC分类号： H01L31/18
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/124 , H01L27/1255
摘要： A substrate comprising a thin-film-transistor (TFT) region, a pixel region, a gate-line region and a data-line region is provided. A transparent conductive layer and a first metal layer are orderly formed on the substrate. A conductive stack layer is formed within each of the TFT/pixel/gate-line regions and the end of the data-line region. Next, a first insulating layer and a semiconductor layer are orderly formed, and a patterned first insulating layer and a patterned semiconductor layer are formed above the conductive stack layer within the TFT region. Then, a second metal layer and a first photoresist layer are respectively formed. Afterwards, the second and the first metal layers are patterned by using the first photoresist layer as a photomask. Finally, the first photoresist layer is reflowed by heat, and part of the reflowed first photoresist layer covers a channel formed within the TFT region.
摘要翻译：提供了包括薄膜晶体管（TFT）区域，像素区域，栅极线区域和数据线区域的衬底。在衬底上有序地形成透明导电层和第一金属层。在每个TFT /像素/栅极线区域和数据线区域的末端中形成导电堆叠层。接下来，有序地形成第一绝缘层和半导体层，并且在TFT区域内的导电堆叠层的上方形成图案化的第一绝缘层和图案化半导体层。然后，分别形成第二金属层和第一光致抗蚀剂层。之后，通过使用第一光致抗蚀剂层作为光掩模来对第二和第一金属层进行构图。最后，第一光致抗蚀剂层通过热回流，并且回流的第一光致抗蚀剂层的一部分覆盖形成在TFT区域内的沟道。

2. 发明授权

US08143624B2 Display device and method of manufacturing the same 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US08143624B2
公开(公告)日：2012-03-27
申请号：US12076297
申请日：2008-03-17
申请人： Han-Tu Lin , Chien-Hung Chen , Shiun-Chang Jan
发明人： Han-Tu Lin , Chien-Hung Chen , Shiun-Chang Jan
IPC分类号： H01L27/14
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/124 , H01L27/1255
摘要： A substrate comprising a thin-film-transistor (TFT) region, a pixel region, a gate-line region and a data-line region is provided. A transparent conductive layer and a first metal layer are orderly formed on the substrate. A conductive stack layer is formed within each of the TFT/pixel/gate-line regions and the end of the data-line region. Next, a first insulating layer and a semiconductor layer are orderly formed, and a patterned first insulating layer and a patterned semiconductor layer are formed above the conductive stack layer within the TFT region. Then, a second metal layer and a first photoresist layer are respectively formed. Afterwards, the second and the first metal layers are patterned by using the first photoresist layer as a photomask. Finally, the first photoresist layer is reflowed by heat, and part of the reflowed first photoresist layer covers a channel formed within the TFT region.
摘要翻译：提供了包括薄膜晶体管（TFT）区域，像素区域，栅极线区域和数据线区域的衬底。在衬底上有序地形成透明导电层和第一金属层。在每个TFT /像素/栅极线区域和数据线区域的末端中形成导电堆叠层。接下来，有序地形成第一绝缘层和半导体层，并且在TFT区域内的导电堆叠层的上方形成图案化的第一绝缘层和图案化半导体层。然后，分别形成第二金属层和第一光致抗蚀剂层。之后，通过使用第一光致抗蚀剂层作为光掩模来对第二和第一金属层进行构图。最后，第一光致抗蚀剂层通过热回流，并且回流的第一光致抗蚀剂层的一部分覆盖形成在TFT区域内的沟道。

3. 发明授权

US08084771B2 Bottom-gate thin film transistor and method of fabricating the same 有权
标题翻译：底栅薄膜晶体管及其制造方法
公开(公告)号：US08084771B2
公开(公告)日：2011-12-27
申请号：US12893063
申请日：2010-09-29
申请人： Ya-Hui Peng , Yi-Ya Tseng , Kun-Fu Huang , Chih-Hsien Chen , Han-Tu Lin
发明人： Ya-Hui Peng , Yi-Ya Tseng , Kun-Fu Huang , Chih-Hsien Chen , Han-Tu Lin
IPC分类号： H01L29/04 , H01L31/036 , H01L27/01 , H01L27/12 , H01L31/20
CPC分类号： H01L29/66765 , H01L29/04 , H01L29/452 , H01L29/78678 , H01L29/78696
摘要： A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 1020 atoms/cm3 and 1025 atoms/cm3. A method of fabricating a bottom-gate thin film transistor is also disclosed herein.
摘要翻译：底栅薄膜晶体管包括栅电极，栅极绝缘层和微晶硅层。栅电极设置在基板上。栅极绝缘层由氮化硅构成并且设置在栅电极和基板上。微晶硅层设置在栅极绝缘层上，对应于栅电极，其中栅极绝缘层和微晶硅层之间的接触界面具有多个氧原子，氧原子的浓度范围在1020原子之间 / cm3和1025原子/ cm3。本文还公开了制造底栅薄膜晶体管的方法。

4. 发明申请

US20110169002A1 PIXEL STRUCTURE 审中-公开
标题翻译：像素结构
公开(公告)号：US20110169002A1
公开(公告)日：2011-07-14
申请号：US13052117
申请日：2011-03-21
申请人： Shiun-Chang Jan , Han-Tu Lin
发明人： Shiun-Chang Jan , Han-Tu Lin
IPC分类号： H01L29/04
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A pixel structure includes a substrate, a gate and a pixel electrode that are disposed on the substrate, a patterned dielectric layer and a patterned semiconductor layer disposed on the gate, a source and a drain disposed on two sides of the patterned semiconductor layer respectively, and a passivation layer disposed on the source, the drain and the semiconductor layer. The sidewall surfaces of the source and the drain are completely covered with the passivation layer, but a part of the pixel electrode is exposed by the passivation layer.
摘要翻译：像素结构包括设置在基板上的基板，栅极和像素电极，设置在栅极上的图案化电介质层和图案化半导体层，分别设置在图案化半导体层的两侧上的源极和漏极，以及设置在源极，漏极和半导体层上的钝化层。源极和漏极的侧壁表面被钝化层完全覆盖，但是像素电极的一部分被钝化层暴露。

5. 发明申请

US20110101459A1 Thin Film Transistors and Fabrication Methods Thereof 审中-公开
标题翻译：薄膜晶体管及其制作方法
公开(公告)号：US20110101459A1
公开(公告)日：2011-05-05
申请号：US13005349
申请日：2011-01-12
申请人： Feng-Yuan Gan , Han-Tu Lin
发明人： Feng-Yuan Gan , Han-Tu Lin
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L29/66765 , H01L29/4908 , H01L29/78603
摘要： Thin film transistors and fabrication methods thereof. A gate is formed overlying a portion of a substrate. A first vanadium oxide layer formed overlying the gate and the substrate. A gate-insulating layer is formed overlying the first vanadium oxide layer. A semiconductor layer is formed on a portion of the gate-insulating layer. A source and a drain are formed on a portion of the semiconductor layer.
摘要翻译：薄膜晶体管及其制造方法。形成覆盖衬底的一部分的栅极。形成在栅极和衬底上的第一氧化钒层。形成覆盖第一氧化钒层的栅极绝缘层。半导体层形成在栅极绝缘层的一部分上。源极和漏极形成在半导体层的一部分上。

6. 发明授权

US07898721B2 Method and device for adjusting driving voltage of microelectromechanical optical device 有权
标题翻译：微机电光学装置的驱动电压调整方法及装置
公开(公告)号：US07898721B2
公开(公告)日：2011-03-01
申请号：US11030526
申请日：2005-01-06
申请人： Feng-Yuan Gan , Han-Tu Lin , Jia-Fam Wong
发明人： Feng-Yuan Gan , Han-Tu Lin , Jia-Fam Wong
IPC分类号： G02B26/00
CPC分类号： G09G3/3466 , G09G2310/0275 , G09G2320/041
摘要： A driving voltage adjusting device for a microelectromechanical optical (MEMO) device. The adjusting device comprises a parameter generator and a driving device. The driving device outputs an adjusting driving voltage to the MEMO device to a parameter from the parameter generator.
摘要翻译：一种用于微机电光学（MEMO）装置的驱动电压调节装置。调节装置包括参数发生器和驱动装置。驱动装置向MEMO装置输出调整驱动电压到参数发生器的参数。

7. 发明授权

US07777231B2 Thin film transistor and method for fabricating same 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US07777231B2
公开(公告)日：2010-08-17
申请号：US12432735
申请日：2009-04-29
申请人： Feng-Yuan Gan , Han-Tu Lin
发明人： Feng-Yuan Gan , Han-Tu Lin
IPC分类号： H01L21/02
CPC分类号： H01L29/66765 , H01L29/4908 , H01L29/78609
摘要： A method for forming a thin film transistor on a substrate is disclosed. A gate electrode and a gate insulation layer are disposed on a surface of the substrate. A deposition process is performed by utilizing hydrogen diluted silane to form a silicon-contained thin film on the gate insulation layer first. A hydrogen plasma etching process is thereafter performed. The deposition process and the etching process are repeated for at least one time to form an interface layer. Finally, an amorphous silicon layer, n+ doped Si layers, a source electrode, and a drain electrode are formed on the interface layer.
摘要翻译：公开了一种在衬底上形成薄膜晶体管的方法。栅电极和栅极绝缘层设置在基板的表面上。首先通过利用氢稀释的硅烷在栅极绝缘层上形成含硅薄膜来进行沉积工艺。此后执行氢等离子体蚀刻工艺。重复沉积工艺和蚀刻工艺至少一次以形成界面层。最后，在界面层上形成非晶硅层，n +掺杂Si层，源电极和漏电极。

8. 发明授权

US07682884B2 Method for fabricating pixel structure 有权
标题翻译：制造像素结构的方法
公开(公告)号：US07682884B2
公开(公告)日：2010-03-23
申请号：US12017342
申请日：2008-01-22
申请人： Han-Tu Lin , Chih-Chun Yang , Ming-Yuan Huang , Chih-Hung Shih , Ta-Wen Liao , Chia-Chi Tsai
发明人： Han-Tu Lin , Chih-Chun Yang , Ming-Yuan Huang , Chih-Hung Shih , Ta-Wen Liao , Chia-Chi Tsai
IPC分类号： H01L21/00
CPC分类号： H01L27/14692 , H01L27/124 , H01L27/1288
摘要： A method for fabricating a pixel structure using a laser ablation process is provided. This fabrication method forms a gate, a channel layer, a source, a drain, a passivation layer, and a pixel electrode sequentially by using a laser ablation process. Particularly, the fabrication method is not similar to a photolithography and etching process, so as to reduce the complicated photolithography and etching processes, such as spin coating process, soft-bake, hard-bake, exposure, developing, etching, and stripping. Therefore, the fabrication method simplifies the process and thus reduces the fabrication cost.
摘要翻译：提供了一种使用激光烧蚀工艺制造像素结构的方法。该制造方法通过使用激光烧蚀工艺依次形成栅极，沟道层，源极，漏极，钝化层和像素电极。特别地，制造方法与光刻和蚀刻工艺不同，从而减少旋涂，软烘烤，硬烘烤，曝光，显影，蚀刻和剥离等复杂的光刻和蚀刻工艺。因此，制造方法简化了工艺，从而降低了制造成本。

9. 发明授权

US07679088B2 Thin-film transistor and fabrication method thereof 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US07679088B2
公开(公告)日：2010-03-16
申请号：US12146479
申请日：2008-06-26
申请人： Han-Tu Lin
发明人： Han-Tu Lin
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/66765
摘要： A fabrication method of a TFT includes successively forming four thin films containing a first conductive layer, an insulation layer, a semiconductor layer, and a second conductive layer on a substrate, performing a first PEP process to pattern the four thin films for forming a semiconductor island and a gate electrode with the semiconductor layer and the first conductive layer respectively. Then, a laser ablation process is performed to define a channel pattern in the four thin films and remove a portion of the second conductive layer so that unconnected source electrode and drain electrode are formed with the second conductive layer.
摘要翻译： TFT的制造方法包括在基板上依次形成包含第一导电层，绝缘层，半导体层和第二导电层的四个薄膜，执行第一PEP工艺以对四个用于形成半导体的薄膜岛和分别具有半导体层和第一导电层的栅电极。然后，执行激光烧蚀处理以限定四个薄膜中的沟道图案，并去除第二导电层的一部分，使得未连接的源电极和漏电极与第二导电层形成。

10. 发明申请

US20090256164A1 Active Device Array Substrate and Method for Fabricating the Same 有权
标题翻译：有源器件阵列基板及其制造方法
公开(公告)号：US20090256164A1
公开(公告)日：2009-10-15
申请号：US12190887
申请日：2008-08-13
申请人： Kuo-Lung Fang , Hsiang-Lin Lin , Han-Tu Lin
发明人： Kuo-Lung Fang , Hsiang-Lin Lin , Han-Tu Lin
IPC分类号： H01L33/00 , H01L21/30
CPC分类号： H01L27/1288 , H01L27/124
摘要： An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate.
摘要翻译：提供一种有源器件阵列衬底及其制造方法。根据本发明，诸如薄膜晶体管，栅极线，栅极焊盘，数据线，数据焊盘和存储电极之类的阵列基板的元件通过形成图案化的第一金属层，绝缘层，图案化半导体层和图案化金属多层。此外，本发明使用选择性蚀刻某些层的方法。使用上述方法，本发明的阵列基板具有一些具有欠切割结构的层，因此可以减少在阵列基板的制造中涉及的耗时且复杂的掩模蚀刻工艺的数量。本发明提供了用于制造阵列基板的相对简单且省时的方法。

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