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1. 发明授权

US08071407B2 Active device array substrate and method for fabricating the same 有权
标题翻译：有源器件阵列衬底及其制造方法
公开(公告)号：US08071407B2
公开(公告)日：2011-12-06
申请号：US12835874
申请日：2010-07-14
申请人： Kuo-Lung Fang , Hsiang-Lin Lin , Han-Tu Lin
发明人： Kuo-Lung Fang , Hsiang-Lin Lin , Han-Tu Lin
IPC分类号： H01L21/28
CPC分类号： H01L27/1288 , H01L27/124
摘要： An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate.
摘要翻译：提供一种有源器件阵列衬底及其制造方法。根据本发明，诸如薄膜晶体管，栅极线，栅极焊盘，数据线，数据焊盘和存储电极之类的阵列基板的元件通过形成图案化的第一金属层，绝缘层，图案化半导体层和图案化金属多层。此外，本发明使用选择性蚀刻某些层的方法。使用上述方法，本发明的阵列基板具有一些具有欠切割结构的层，因此可以减少与制造阵列基板有关的耗时且复杂的掩模蚀刻工艺的数量。本发明提供了用于制造阵列基板的相对简单且省时的方法。

2. 发明申请

US20110284074A1 PHOTOVOLTAIC CELL 审中-公开
标题翻译：光伏电池
公开(公告)号：US20110284074A1
公开(公告)日：2011-11-24
申请号：US12891721
申请日：2010-09-27
申请人： Chee-Wee Liu , Wei-Shuo Ho , Yen-Yu Chen , Chun-Yuan Ku , Chien-Jen Chen , Han-Tu Lin , Shuo-Wei Liang
发明人： Chee-Wee Liu , Wei-Shuo Ho , Yen-Yu Chen , Chun-Yuan Ku , Chien-Jen Chen , Han-Tu Lin , Shuo-Wei Liang
IPC分类号： H01L31/0376
CPC分类号： H01L31/0747 , Y02E10/50
摘要： A photovoltaic cell includes a first type doped mono-crystalline silicon substrate, an intrinsic amorphous silicon layer, a second type doped amorphous silicon layer, a first type doped crystalline Ge-containing layer, and a pair of electrodes. The first type doped mono-crystalline silicon substrate has a front surface and a rear surface. The intrinsic amorphous silicon layer is disposed on the front surface. The second type doped amorphous silicon layer is disposed on the intrinsic amorphous silicon layer. The first type doped crystalline Ge-containing layer is disposed on the rear surface. The pair of electrodes are electrically connected to the second type doped amorphous silicon layer and first type doped crystalline Ge-containing layer, respectively.
摘要翻译：光伏电池包括第一掺杂单晶硅衬底，本征非晶硅层，第二掺杂非晶硅层，第一掺杂晶体Ge含量层和一对电极。第一种掺杂单晶硅衬底具有前表面和后表面。本征非晶硅层设置在前表面上。第二类掺杂非晶硅层设置在本征非晶硅层上。第一类型的掺杂结晶Ge含量层设置在后表面上。该对电极分别电连接到第二类掺杂非晶硅层和第一掺杂结晶Ge含量层。

3. 发明申请

US20110117707A1 PIXEL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：像素结构及其制造方法
公开(公告)号：US20110117707A1
公开(公告)日：2011-05-19
申请号：US13013887
申请日：2011-01-26
申请人： Han-Tu Lin , Chien-Hung Chen
发明人： Han-Tu Lin , Chien-Hung Chen
IPC分类号： H01L21/336
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A method for manufacturing a pixel structure is provided. First, a first mask process is performed to form a patterned first metal layer on a substrate, wherein the patterned first metal layer includes a gate. Next, a second mask process is performed to form a patterned insulating layer and a patterned semiconductor layer over the gate, wherein the patterned insulating layer is disposed on the patterned first metal layer, and the patterned semiconductor layer is disposed on the patterned insulating layer. Then, a third mask process is performed to define a thin film transistor (TFT) and a pixel electrode connected thereto and to form a passivation layer to cover the TFT.
摘要翻译：提供了一种用于制造像素结构的方法。首先，执行第一掩模处理以在基板上形成图案化的第一金属层，其中图案化的第一金属层包括栅极。接下来，执行第二掩模处理以在栅极上形成图案化绝缘层和图案化半导体层，其中图案化绝缘层设置在图案化的第一金属层上，并且图案化的半导体层设置在图案化的绝缘层上。然后，执行第三掩模处理以限定连接到其上的薄膜晶体管（TFT）和像素电极，并形成覆盖TFT的钝化层。

4. 发明申请

US20110012114A1 Bottom-Gate Thin Film Transistor and Method of Fabricating the Same 有权
标题翻译：底栅薄膜晶体管及其制造方法
公开(公告)号：US20110012114A1
公开(公告)日：2011-01-20
申请号：US12893063
申请日：2010-09-29
申请人： Ya-Hui Peng , Yi-Ya Tseng , Kun-Fu Huang , Chih-Hsien Chen , Han-Tu Lin
发明人： Ya-Hui Peng , Yi-Ya Tseng , Kun-Fu Huang , Chih-Hsien Chen , Han-Tu Lin
IPC分类号： H01L29/786
CPC分类号： H01L29/66765 , H01L29/04 , H01L29/452 , H01L29/78678 , H01L29/78696
摘要： A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 1020 atoms/cm3 and 1025 atoms/cm3. A method of fabricating a bottom-gate thin film transistor is also disclosed herein.
摘要翻译：底栅薄膜晶体管包括栅电极，栅极绝缘层和微晶硅层。栅电极设置在基板上。栅极绝缘层由氮化硅构成并且设置在栅电极和基板上。微晶硅层设置在栅极绝缘层上，对应于栅电极，其中栅极绝缘层和微晶硅层之间的接触界面具有多个氧原子，氧原子的浓度范围在1020原子之间 / cm3和1025原子/ cm3。本文还公开了制造底栅薄膜晶体管的方法。

5. 发明申请

US20100279450A1 Active Device Array Substrate and Method for Fabricating the Same 有权
标题翻译：有源器件阵列基板及其制造方法
公开(公告)号：US20100279450A1
公开(公告)日：2010-11-04
申请号：US12835874
申请日：2010-07-14
申请人： Kuo-Lung Fang , Hsiang-Lin Lin , Han-Tu Lin
发明人： Kuo-Lung Fang , Hsiang-Lin Lin , Han-Tu Lin
IPC分类号： H01L21/28
CPC分类号： H01L27/1288 , H01L27/124
摘要： An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate.
摘要翻译：提供一种有源器件阵列衬底及其制造方法。根据本发明，诸如薄膜晶体管，栅极线，栅极焊盘，数据线，数据焊盘和存储电极之类的阵列基板的元件通过形成图案化的第一金属层，绝缘层，图案化半导体层和图案化金属多层。此外，本发明使用选择性蚀刻某些层的方法。使用上述方法，本发明的阵列基板具有一些具有欠切割结构的层，因此可以减少在阵列基板的制造中涉及的耗时且复杂的掩模蚀刻工艺的数量。本发明提供了用于制造阵列基板的相对简单且省时的方法。

6. 发明授权

US07754547B2 Method of manufacturing active matrix array structure 有权
标题翻译：有源矩阵阵列结构的制造方法
公开(公告)号：US07754547B2
公开(公告)日：2010-07-13
申请号：US12102027
申请日：2008-04-14
申请人： Wei-Sheng Yu , Kuo-Lung Fang , Hsiang-Lin Lin , Hsien-Chieh Tseng , Han-Tu Lin
发明人： Wei-Sheng Yu , Kuo-Lung Fang , Hsiang-Lin Lin , Hsien-Chieh Tseng , Han-Tu Lin
IPC分类号： H01L21/00
CPC分类号： H01L27/124 , H01L27/1248 , H01L27/1288
摘要： An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.
摘要翻译：设置在基板上的有源矩阵阵列结构包括第一图案化导电层，图案化栅极绝缘层，图案化半导体层，第二图案化导电层，图案化外涂层和透明导电层。图案化栅极绝缘层具有暴露第一图案化导电层的一部分的第一开口。图案化的半导体层设置在图案化的栅极绝缘层上。第二图案化导电层设置在图案化的半导体层上。图案化的外涂层具有暴露第一图案化导电层的一部分和第二图案化导电层的一部分的第二开口。透明导电层完全设置在基板上。设置在第一开口和第二开口中的透明导电层在基板和图案化外涂层之间的位置处断开。

7. 发明申请

US20100055853A1 METHOD FOR MANUFACTURING PIXEL STRUCTURE 有权
标题翻译：制造像素结构的方法
公开(公告)号：US20100055853A1
公开(公告)日：2010-03-04
申请号：US12617712
申请日：2009-11-12
申请人： Chih-Chun Yang , Ming-Yuan Huang , Han-Tu Lin , Chih-Hung Shih , Ta-Wen Liao , Kuo-Lung Fang , Chia-Chi Tsai
发明人： Chih-Chun Yang , Ming-Yuan Huang , Han-Tu Lin , Chih-Hung Shih , Ta-Wen Liao , Kuo-Lung Fang , Chia-Chi Tsai
IPC分类号： H01L21/336
CPC分类号： H01L27/1248 , H01L27/1288
摘要： A method for manufacturing a pixel structure is provided. A gate and a gate insulating layer are sequentially formed on a substrate. A semiconductor layer and a second metal layer are sequentially formed on the gate insulating layer. The semiconductor layer and the second metal layer are patterned to form a channel layer, a source and a drain by using a patterned photoresist layer formed thereon, wherein the source and drain are disposed on a portion of the channel layer. The gate, channel, source and drain form a thin film transistor. A passivation layer is formed on the patterned photoresist layer, the gate insulating layer and the thin film transistor. Then, the patterned photoresist layer is removed, such that the passivation layer thereon is removed simultaneously to form a patterned passivation layer and the drain is exposed. A pixel electrode is formed on the patterned passivation layer and the drain.
摘要翻译：提供了一种用于制造像素结构的方法。栅极和栅极绝缘层依次形成在基板上。半导体层和第二金属层依次形成在栅极绝缘层上。通过使用形成在其上的图案化光致抗蚀剂层，将半导体层和第二金属层图案化以形成沟道层，源极和漏极，其中源极和漏极设置在沟道层的一部分上。栅极，沟道，源极和漏极形成薄膜晶体管。在图案化的光致抗蚀剂层，栅极绝缘层和薄膜晶体管上形成钝化层。然后，去除图案化的光致抗蚀剂层，使得其上的钝化层被同时去除以形成图案化的钝化层，并且漏极被暴露。在图案化的钝化层和漏极上形成像素电极。

8. 发明申请

US20100051954A1 Pixel structure and method for manufacturing the same 有权
标题翻译：像素结构及其制造方法
公开(公告)号：US20100051954A1
公开(公告)日：2010-03-04
申请号：US12591019
申请日：2009-11-05
申请人： Han-Tu Lin , Chien-Hung Chen
发明人： Han-Tu Lin , Chien-Hung Chen
IPC分类号： H01L33/00 , H01L31/0224
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A method for manufacturing a pixel structure is provided. First, a first mask process is performed to form a patterned first metal layer on a substrate, wherein the patterned first metal layer includes a gate. Next, a second mask process is performed to form a patterned insulating layer and a patterned semiconductor layer over the gate, wherein the patterned insulating layer is disposed on the patterned first metal layer, and the patterned semiconductor layer is disposed on the patterned insulating layer. Then, a third mask process is performed to define a thin film transistor (TFT) and a pixel electrode connected thereto and to form a passivation layer to cover the TFT.
摘要翻译：提供了一种用于制造像素结构的方法。首先，执行第一掩模处理以在基板上形成图案化的第一金属层，其中图案化的第一金属层包括栅极。接下来，执行第二掩模处理以在栅极上形成图案化绝缘层和图案化半导体层，其中图案化绝缘层设置在图案化的第一金属层上，并且图案化的半导体层设置在图案化的绝缘层上。然后，执行第三掩模处理以限定连接到其上的薄膜晶体管（TFT）和像素电极，并形成覆盖TFT的钝化层。

9. 发明申请

US20090148972A1 METHOD FOR FABRICATING PIXEL STRUCTURE 有权
标题翻译：制造像素结构的方法
公开(公告)号：US20090148972A1
公开(公告)日：2009-06-11
申请号：US12105279
申请日：2008-04-18
申请人： Kuo-Lung Fang , Chih-Chun Yang , Ming-Yuan Huang , Han-Tu Lin , Chih-Hung Shih , Ta-Wen Liao , Shiun-Chang Jan , Chia-Chi Tsai
发明人： Kuo-Lung Fang , Chih-Chun Yang , Ming-Yuan Huang , Han-Tu Lin , Chih-Hung Shih , Ta-Wen Liao , Shiun-Chang Jan , Chia-Chi Tsai
IPC分类号： H01L21/00
CPC分类号： H01L27/1248 , H01L27/1255 , H01L27/1288
摘要： A method for fabricating a pixel structure includes following steps. First, a substrate is provided. Next, a first conductive layer is formed on the substrate. Next, a first shadow mask is disposed over the first conductive layer. Next, a laser is applied through the first shadow mask to irradiate the first conductive layer to form a gate. Next, a gate dielectric layer is formed on the substrate to cover the gate. After that, a channel layer, a source and a drain are simultaneously formed on the gate dielectric layer over the gate, wherein the gate, the channel layer, the source and the drain together form a thin film transistor. A patterned passivation layer is formed on the thin film transistor and the patterned passivation layer exposes a part of the drain. Furthermore, a pixel electrode electrically connecting to the drain is formed.
摘要翻译：一种用于制造像素结构的方法包括以下步骤。首先，提供基板。接下来，在基板上形成第一导电层。接下来，在第一导电层上设置第一荫罩。接下来，通过第一荫罩施加激光以照射第一导电层以形成栅极。接下来，在基板上形成栅电介质层以覆盖栅极。之后，沟道层，源极和漏极同时形成在栅极上的栅极电介质层上，其中栅极，沟道层，源极和漏极一起形成薄膜晶体管。图案化的钝化层形成在薄膜晶体管上，并且图案化的钝化层露出一部分漏极。此外，形成电连接到漏极的像素电极。

10. 发明申请

US20090101902A1 Display device and method of manufacturing the same 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US20090101902A1
公开(公告)日：2009-04-23
申请号：US12076297
申请日：2008-03-17
申请人： Han-Tu Lin , Chien-Hung Chen , Shiun-Chang Jan
发明人： Han-Tu Lin , Chien-Hung Chen , Shiun-Chang Jan
IPC分类号： H01L33/00 , H01L21/00
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/124 , H01L27/1255
摘要： A substrate comprising a thin-film-transistor (TFT) region, a pixel region, a gate-line region and a data-line region is provided. A transparent conductive layer and a first metal layer are orderly formed on the substrate. A conductive stack layer is formed within each of the TFT/pixel/gate-line regions and the end of the data-line region. Next, a first insulating layer and a semiconductor layer are orderly formed, and a patterned first insulating layer and a patterned semiconductor layer are formed above the conductive stack layer within the TFT region. Then, a second metal layer and a first photoresist layer are respectively formed. Afterwards, the second and the first metal layers are patterned by using the first photoresist layer as a photomask. Finally, the first photoresist layer is reflowed by heat, and part of the reflowed first photoresist layer covers a channel formed within the TFT region.
摘要翻译：提供了包括薄膜晶体管（TFT）区域，像素区域，栅极线区域和数据线区域的衬底。在衬底上有序地形成透明导电层和第一金属层。在每个TFT /像素/栅极线区域和数据线区域的末端中形成导电堆叠层。接下来，有序地形成第一绝缘层和半导体层，并且在TFT区域内的导电堆叠层的上方形成图案化的第一绝缘层和图案化半导体层。然后，分别形成第二金属层和第一光致抗蚀剂层。之后，通过使用第一光致抗蚀剂层作为光掩模来对第二和第一金属层进行构图。最后，第一光致抗蚀剂层通过热回流，并且回流的第一光致抗蚀剂层的一部分覆盖形成在TFT区域内的沟道。

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