专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08071407B2 Active device array substrate and method for fabricating the same 有权
标题翻译：有源器件阵列衬底及其制造方法
公开(公告)号：US08071407B2
公开(公告)日：2011-12-06
申请号：US12835874
申请日：2010-07-14
申请人： Kuo-Lung Fang , Hsiang-Lin Lin , Han-Tu Lin
发明人： Kuo-Lung Fang , Hsiang-Lin Lin , Han-Tu Lin
IPC分类号： H01L21/28
CPC分类号： H01L27/1288 , H01L27/124
摘要： An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate.
摘要翻译：提供一种有源器件阵列衬底及其制造方法。根据本发明，诸如薄膜晶体管，栅极线，栅极焊盘，数据线，数据焊盘和存储电极之类的阵列基板的元件通过形成图案化的第一金属层，绝缘层，图案化半导体层和图案化金属多层。此外，本发明使用选择性蚀刻某些层的方法。使用上述方法，本发明的阵列基板具有一些具有欠切割结构的层，因此可以减少与制造阵列基板有关的耗时且复杂的掩模蚀刻工艺的数量。本发明提供了用于制造阵列基板的相对简单且省时的方法。

2. 发明申请

US20100279450A1 Active Device Array Substrate and Method for Fabricating the Same 有权
标题翻译：有源器件阵列基板及其制造方法
公开(公告)号：US20100279450A1
公开(公告)日：2010-11-04
申请号：US12835874
申请日：2010-07-14
申请人： Kuo-Lung Fang , Hsiang-Lin Lin , Han-Tu Lin
发明人： Kuo-Lung Fang , Hsiang-Lin Lin , Han-Tu Lin
IPC分类号： H01L21/28
CPC分类号： H01L27/1288 , H01L27/124
摘要： An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate.
摘要翻译：提供一种有源器件阵列衬底及其制造方法。根据本发明，诸如薄膜晶体管，栅极线，栅极焊盘，数据线，数据焊盘和存储电极之类的阵列基板的元件通过形成图案化的第一金属层，绝缘层，图案化半导体层和图案化金属多层。此外，本发明使用选择性蚀刻某些层的方法。使用上述方法，本发明的阵列基板具有一些具有欠切割结构的层，因此可以减少在阵列基板的制造中涉及的耗时且复杂的掩模蚀刻工艺的数量。本发明提供了用于制造阵列基板的相对简单且省时的方法。

3. 发明授权

US07754547B2 Method of manufacturing active matrix array structure 有权
标题翻译：有源矩阵阵列结构的制造方法
公开(公告)号：US07754547B2
公开(公告)日：2010-07-13
申请号：US12102027
申请日：2008-04-14
申请人： Wei-Sheng Yu , Kuo-Lung Fang , Hsiang-Lin Lin , Hsien-Chieh Tseng , Han-Tu Lin
发明人： Wei-Sheng Yu , Kuo-Lung Fang , Hsiang-Lin Lin , Hsien-Chieh Tseng , Han-Tu Lin
IPC分类号： H01L21/00
CPC分类号： H01L27/124 , H01L27/1248 , H01L27/1288
摘要： An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.
摘要翻译：设置在基板上的有源矩阵阵列结构包括第一图案化导电层，图案化栅极绝缘层，图案化半导体层，第二图案化导电层，图案化外涂层和透明导电层。图案化栅极绝缘层具有暴露第一图案化导电层的一部分的第一开口。图案化的半导体层设置在图案化的栅极绝缘层上。第二图案化导电层设置在图案化的半导体层上。图案化的外涂层具有暴露第一图案化导电层的一部分和第二图案化导电层的一部分的第二开口。透明导电层完全设置在基板上。设置在第一开口和第二开口中的透明导电层在基板和图案化外涂层之间的位置处断开。

4. 发明授权

US07842954B2 Active matrix array structure 有权
标题翻译：主动矩阵阵列结构
公开(公告)号：US07842954B2
公开(公告)日：2010-11-30
申请号：US12775493
申请日：2010-05-07
申请人： Wei-Sheng Yu , Kuo-Lung Fang , Hsiang-Lin Lin , Hsien-Chieh Tseng , Han-Tu Lin
发明人： Wei-Sheng Yu , Kuo-Lung Fang , Hsiang-Lin Lin , Hsien-Chieh Tseng , Han-Tu Lin
IPC分类号： H01L33/00
CPC分类号： H01L27/124 , H01L27/1248 , H01L27/1288
摘要： An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.
摘要翻译：设置在基板上的有源矩阵阵列结构包括第一图案化导电层，图案化栅极绝缘层，图案化半导体层，第二图案化导电层，图案化外涂层和透明导电层。图案化栅极绝缘层具有暴露第一图案化导电层的一部分的第一开口。图案化的半导体层设置在图案化的栅极绝缘层上。第二图案化导电层设置在图案化的半导体层上。图案化的外涂层具有暴露第一图案化导电层的一部分和第二图案化导电层的一部分的第二开口。透明导电层完全设置在基板上。设置在第一开口和第二开口中的透明导电层在基板和图案化外涂层之间的位置处断开。

5. 发明授权

US07781776B2 Active device array substrate and method for fabricating the same 有权
标题翻译：有源器件阵列衬底及其制造方法
公开(公告)号：US07781776B2
公开(公告)日：2010-08-24
申请号：US12190887
申请日：2008-08-13
申请人： Kuo-Lung Fang , Hsiang-Lin Lin , Han-Tu Lin
发明人： Kuo-Lung Fang , Hsiang-Lin Lin , Han-Tu Lin
IPC分类号： H01L21/30
CPC分类号： H01L27/1288 , H01L27/124
摘要： An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate.
摘要翻译：提供一种有源器件阵列衬底及其制造方法。根据本发明，诸如薄膜晶体管，栅极线，栅极焊盘，数据线，数据焊盘和存储电极之类的阵列基板的元件通过形成图案化的第一金属层，绝缘层，图案化半导体层和图案化金属多层。此外，本发明使用选择性蚀刻某些层的方法。使用上述方法，本发明的阵列基板具有一些具有欠切割结构的层，因此可以减少与制造阵列基板有关的耗时且复杂的掩模蚀刻工艺的数量。本发明提供了用于制造阵列基板的相对简单且省时的方法。

6. 发明申请

US20090173943A1 ACTIVE MATRIX ARRAY STRUCTURE AND MANUFACTURING MEHTOD THEREOF 有权
标题翻译：主动矩阵阵列结构及其制造方法
公开(公告)号：US20090173943A1
公开(公告)日：2009-07-09
申请号：US12102027
申请日：2008-04-14
申请人： Wei-Sheng Yu , Kuo-Lung Fang , Hsiang-Lin Lin , Hsien-Chieh Tseng , Han-Tu Lin
发明人： Wei-Sheng Yu , Kuo-Lung Fang , Hsiang-Lin Lin , Hsien-Chieh Tseng , Han-Tu Lin
IPC分类号： H01L33/00
CPC分类号： H01L27/124 , H01L27/1248 , H01L27/1288
摘要： An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.
摘要翻译：设置在基板上的有源矩阵阵列结构包括第一图案化导电层，图案化栅极绝缘层，图案化半导体层，第二图案化导电层，图案化外涂层和透明导电层。图案化栅极绝缘层具有暴露第一图案化导电层的一部分的第一开口。图案化的半导体层设置在图案化的栅极绝缘层上。第二图案化导电层设置在图案化的半导体层上。图案化的外涂层具有暴露第一图案化导电层的一部分和第二图案化导电层的一部分的第二开口。透明导电层完全设置在基板上。设置在第一开口和第二开口中的透明导电层在基板和图案化外涂层之间的位置处断开。

7. 发明申请

US20090256164A1 Active Device Array Substrate and Method for Fabricating the Same 有权
标题翻译：有源器件阵列基板及其制造方法
公开(公告)号：US20090256164A1
公开(公告)日：2009-10-15
申请号：US12190887
申请日：2008-08-13
申请人： Kuo-Lung Fang , Hsiang-Lin Lin , Han-Tu Lin
发明人： Kuo-Lung Fang , Hsiang-Lin Lin , Han-Tu Lin
IPC分类号： H01L33/00 , H01L21/30
CPC分类号： H01L27/1288 , H01L27/124
摘要： An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate.
摘要翻译：提供一种有源器件阵列衬底及其制造方法。根据本发明，诸如薄膜晶体管，栅极线，栅极焊盘，数据线，数据焊盘和存储电极之类的阵列基板的元件通过形成图案化的第一金属层，绝缘层，图案化半导体层和图案化金属多层。此外，本发明使用选择性蚀刻某些层的方法。使用上述方法，本发明的阵列基板具有一些具有欠切割结构的层，因此可以减少在阵列基板的制造中涉及的耗时且复杂的掩模蚀刻工艺的数量。本发明提供了用于制造阵列基板的相对简单且省时的方法。

8. 发明申请

US20100213464A1 ACTIVE MATRIX ARRAY STRUCTURE 有权
标题翻译：主动矩阵阵列结构
公开(公告)号：US20100213464A1
公开(公告)日：2010-08-26
申请号：US12775493
申请日：2010-05-07
申请人： Wei-Sheng Yu , Kuo-Lung Fang , Hsiang-Lin Lin , Hsien-Chieh Tseng , Han-Tu Lin
发明人： Wei-Sheng Yu , Kuo-Lung Fang , Hsiang-Lin Lin , Hsien-Chieh Tseng , Han-Tu Lin
IPC分类号： H01L33/16
CPC分类号： H01L27/124 , H01L27/1248 , H01L27/1288
摘要： An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.
摘要翻译：设置在基板上的有源矩阵阵列结构包括第一图案化导电层，图案化栅极绝缘层，图案化半导体层，第二图案化导电层，图案化外涂层和透明导电层。图案化栅极绝缘层具有暴露第一图案化导电层的一部分的第一开口。图案化的半导体层设置在图案化的栅极绝缘层上。第二图案化导电层设置在图案化的半导体层上。图案化的外涂层具有暴露第一图案化导电层的一部分和第二图案化导电层的一部分的第二开口。透明导电层完全设置在基板上。设置在第一开口和第二开口中的透明导电层在基板和图案化外涂层之间的位置处断开。

9. 发明申请

US20100055853A1 METHOD FOR MANUFACTURING PIXEL STRUCTURE 有权
标题翻译：制造像素结构的方法
公开(公告)号：US20100055853A1
公开(公告)日：2010-03-04
申请号：US12617712
申请日：2009-11-12
申请人： Chih-Chun Yang , Ming-Yuan Huang , Han-Tu Lin , Chih-Hung Shih , Ta-Wen Liao , Kuo-Lung Fang , Chia-Chi Tsai
发明人： Chih-Chun Yang , Ming-Yuan Huang , Han-Tu Lin , Chih-Hung Shih , Ta-Wen Liao , Kuo-Lung Fang , Chia-Chi Tsai
IPC分类号： H01L21/336
CPC分类号： H01L27/1248 , H01L27/1288
摘要： A method for manufacturing a pixel structure is provided. A gate and a gate insulating layer are sequentially formed on a substrate. A semiconductor layer and a second metal layer are sequentially formed on the gate insulating layer. The semiconductor layer and the second metal layer are patterned to form a channel layer, a source and a drain by using a patterned photoresist layer formed thereon, wherein the source and drain are disposed on a portion of the channel layer. The gate, channel, source and drain form a thin film transistor. A passivation layer is formed on the patterned photoresist layer, the gate insulating layer and the thin film transistor. Then, the patterned photoresist layer is removed, such that the passivation layer thereon is removed simultaneously to form a patterned passivation layer and the drain is exposed. A pixel electrode is formed on the patterned passivation layer and the drain.
摘要翻译：提供了一种用于制造像素结构的方法。栅极和栅极绝缘层依次形成在基板上。半导体层和第二金属层依次形成在栅极绝缘层上。通过使用形成在其上的图案化光致抗蚀剂层，将半导体层和第二金属层图案化以形成沟道层，源极和漏极，其中源极和漏极设置在沟道层的一部分上。栅极，沟道，源极和漏极形成薄膜晶体管。在图案化的光致抗蚀剂层，栅极绝缘层和薄膜晶体管上形成钝化层。然后，去除图案化的光致抗蚀剂层，使得其上的钝化层被同时去除以形成图案化的钝化层，并且漏极被暴露。在图案化的钝化层和漏极上形成像素电极。

10. 发明申请

US20090148972A1 METHOD FOR FABRICATING PIXEL STRUCTURE 有权
标题翻译：制造像素结构的方法
公开(公告)号：US20090148972A1
公开(公告)日：2009-06-11
申请号：US12105279
申请日：2008-04-18
申请人： Kuo-Lung Fang , Chih-Chun Yang , Ming-Yuan Huang , Han-Tu Lin , Chih-Hung Shih , Ta-Wen Liao , Shiun-Chang Jan , Chia-Chi Tsai
发明人： Kuo-Lung Fang , Chih-Chun Yang , Ming-Yuan Huang , Han-Tu Lin , Chih-Hung Shih , Ta-Wen Liao , Shiun-Chang Jan , Chia-Chi Tsai
IPC分类号： H01L21/00
CPC分类号： H01L27/1248 , H01L27/1255 , H01L27/1288
摘要： A method for fabricating a pixel structure includes following steps. First, a substrate is provided. Next, a first conductive layer is formed on the substrate. Next, a first shadow mask is disposed over the first conductive layer. Next, a laser is applied through the first shadow mask to irradiate the first conductive layer to form a gate. Next, a gate dielectric layer is formed on the substrate to cover the gate. After that, a channel layer, a source and a drain are simultaneously formed on the gate dielectric layer over the gate, wherein the gate, the channel layer, the source and the drain together form a thin film transistor. A patterned passivation layer is formed on the thin film transistor and the patterned passivation layer exposes a part of the drain. Furthermore, a pixel electrode electrically connecting to the drain is formed.
摘要翻译：一种用于制造像素结构的方法包括以下步骤。首先，提供基板。接下来，在基板上形成第一导电层。接下来，在第一导电层上设置第一荫罩。接下来，通过第一荫罩施加激光以照射第一导电层以形成栅极。接下来，在基板上形成栅电介质层以覆盖栅极。之后，沟道层，源极和漏极同时形成在栅极上的栅极电介质层上，其中栅极，沟道层，源极和漏极一起形成薄膜晶体管。图案化的钝化层形成在薄膜晶体管上，并且图案化的钝化层露出一部分漏极。此外，形成电连接到漏极的像素电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式