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1. 发明申请

US20130086541A1 SYSTEM AND METHOD FOR AUTOMATED REAL-TIME DESIGN CHECKING 有权
标题翻译：自动实时设计检查系统与方法
公开(公告)号：US20130086541A1
公开(公告)日：2013-04-04
申请号：US13248914
申请日：2011-09-29
申请人： Wilbur Luo , Olivier Pribetich , Olivier Omedes , Roland Ruehl , Ya-Chieh Lai , Frank E. Gennari
发明人： Wilbur Luo , Olivier Pribetich , Olivier Omedes , Roland Ruehl , Ya-Chieh Lai , Frank E. Gennari
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5022
摘要： Systems and methods for real-time design checking of an integrated circuit design, include the operations of receiving at a design tool, design elements of an integrated circuit design entered by an integrated circuit designer; the design tool performing real-time design checks on the design elements as they are entered by the integrated circuit designer to determine whether a design element violates a design rule; when the design tool detects a violation of a design rule based on the design checks alerting the integrated circuit designer; and the design tool presenting a correction to correct the violation of the design rule. The real-time design checks can include, comparing each design element to one or more known non-compliant design elements stored in a database to determine whether a non-compliant design element was entered or is being entered by the integrated circuit designer.
摘要翻译：集成电路设计的实时设计检查的系统和方法包括在设计工具接收的操作，由集成电路设计者输入的集成电路设计的设计元素; 设计工具对集成电路设计人员输入的设计元素执行实时设计检查，以确定设计元素是否违反设计规则; 当设计工具基于设计检查来检测到违反设计规则时，提醒集成电路设计者; 并且设计工具提出纠正以纠正违反设计规则的情况。实时设计检查可以包括将每个设计元素与存储在数据库中的一个或多个已知的非兼容设计元素进行比较，以确定集成电路设计者是否输入了或正在被集成电路设计者输入。

2. 发明授权

US08807948B2 System and method for automated real-time design checking 有权
标题翻译：用于自动化实时设计检查的系统和方法
公开(公告)号：US08807948B2
公开(公告)日：2014-08-19
申请号：US13248914
申请日：2011-09-29
申请人： Wilbur Luo , Olivier Pribetich , Olivier Omedes , Roland Ruehl , Ya-Chieh Lai , Frank E. Gennari
发明人： Wilbur Luo , Olivier Pribetich , Olivier Omedes , Roland Ruehl , Ya-Chieh Lai , Frank E. Gennari
IPC分类号： B63H1/06
CPC分类号： G06F17/5081 , G06F17/5022
摘要： Systems and methods for real-time design checking of an integrated circuit design, include the operations of receiving at a design tool, design elements of an integrated circuit design entered by an integrated circuit designer; the design tool performing real-time design checks on the design elements as they are entered by the integrated circuit designer to determine whether a design element violates a design rule; when the design tool detects a violation of a design rule based on the design checks alerting the integrated circuit designer; and the design tool presenting a correction to correct the violation of the design rule. The real-time design checks can include, comparing each design element to one or more known non-compliant design elements stored in a database to determine whether a non-compliant design element was entered or is being entered by the integrated circuit designer.
摘要翻译：集成电路设计的实时设计检查的系统和方法包括在设计工具接收的操作，由集成电路设计者输入的集成电路设计的设计元素; 设计工具对集成电路设计人员输入的设计元素执行实时设计检查，以确定设计元素是否违反设计规则; 当设计工具基于设计检查来检测到违反设计规则时，提醒集成电路设计者; 并且设计工具提出纠正以纠正违反设计规则的情况。实时设计检查可以包括将每个设计元素与存储在数据库中的一个或多个已知的非兼容设计元素进行比较，以确定集成电路设计者是否输入了或正在被集成电路设计者输入。

3. 发明授权

US08429582B1 Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing 有权
公开(公告)号：US08429582B1
公开(公告)日：2013-04-23
申请号：US12982693
申请日：2010-12-30
申请人： Ya-Chieh Lai , Frank Gennari , Olivier Omedes , Olivier Pribetich
发明人： Ya-Chieh Lai , Frank Gennari , Olivier Omedes , Olivier Pribetich
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081
摘要： Various embodiments are directed at methods and systems for implementing automatic fixing of a layout, implementing fuzzy pattern replacement, and implementing pattern capturing in a layout of an electronic circuit design. Various processes or modules comprise the act or module of identifying a first pattern from within an electronic circuit layout. The processes or modules also comprise identifying a fixing process or a replacement pattern for the first pattern and the act of performing pattern replacement or pattern fixing on the first pattern. The processes or modules may further comprise the act or module of searching the layout for patterns that match the first pattern, and the act or module of performing pattern replacement of pattern fixing on the patterns that match the first pattern. Some embodiments are also directed at articles of manufacture embodying a sequence of instructions for implementing the processes described here.

4. 发明授权

US08543965B1 Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing 有权
公开(公告)号：US08543965B1
公开(公告)日：2013-09-24
申请号：US12982730
申请日：2010-12-30
申请人： Ya-Chieh Lai , Frank Gennari , Olivier Omedes , Olivier Pribetich
发明人： Ya-Chieh Lai , Frank Gennari , Olivier Omedes , Olivier Pribetich
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081
摘要： Various embodiments are directed at methods and systems for implementing automatic fixing of a layout, implementing fuzzy pattern replacement, and implementing pattern capturing in a layout of an electronic circuit design. Various processes or modules comprise the act or module of identifying a first pattern from within an electronic circuit layout. The processes or modules also comprise identifying a fixing process or a replacement pattern for the first pattern and the act of performing pattern replacement or pattern fixing on the first pattern. The processes or modules may further comprise the act or module of searching the layout for patterns that match the first pattern, and the act or module of performing pattern replacement of pattern fixing on the patterns that match the first pattern. Some embodiments are also directed at articles of manufacture embodying a sequence of instructions for implementing the processes described here.

5. 发明授权

US08516406B1 Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing 有权
标题翻译：智能模式捕捉和布局定位的方法，系统和制造
公开(公告)号：US08516406B1
公开(公告)日：2013-08-20
申请号：US12982712
申请日：2010-12-30
申请人： Ya-Chieh Lai , Frank Gennari , Olivier Omedes , Olivier Pribetich
发明人： Ya-Chieh Lai , Frank Gennari , Olivier Omedes , Olivier Pribetich
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081
摘要： Various embodiments are directed at methods and systems for implementing automatic fixing of a layout, implementing fuzzy pattern replacement, and implementing pattern capturing in a layout of an electronic circuit design. Various processes or modules comprise the act or module of identifying a first pattern from within an electronic circuit layout. The processes or modules also comprise identifying a fixing process or a replacement pattern for the first pattern and the act of performing pattern replacement or pattern fixing on the first pattern. The processes or modules may further comprise the act or module of searching the layout for patterns that match the first pattern, and the act or module of performing pattern replacement of pattern fixing on the patterns that match the first pattern. Some embodiments are also directed at articles of manufacture embodying a sequence of instructions for implementing the processes described here.
摘要翻译：各种实施例涉及用于实现布局的自动固定，实现模糊图案替换以及在电子电路设计的布局中实现图案捕获的方法和系统。各种过程或模块包括从电子电路布局中识别第一图案的动作或模块。处理或模块还包括识别用于第一图案的定影处理或替换图案以及在第一图案上执行图案替换或图案定影的动作。过程或模块还可以包括搜索布局以匹配第一图案的图案的动作或模块，以及在与第一图案匹配的图案上执行图案定影的图案替换的动作或模块。一些实施例还涉及体现用于实现这里描述的过程的指令序列的制造商品。

6. 发明授权

US5416719A Computerized generation of truth tables for sequential and combinatorial cells 失效
标题翻译：计算机生成顺序和组合细胞的真值表
公开(公告)号：US5416719A
公开(公告)日：1995-05-16
申请号：US991915
申请日：1992-12-17
申请人： Olivier Pribetich
发明人： Olivier Pribetich
IPC分类号： G06F17/50 , G06F15/60
CPC分类号： G06F17/5045
摘要： A computerized method of generating a truth table of a cell in a library of circuit cells includes representing basic elements of the cells in a hardware description language, representing each cell as a set of equations in that language and parsing the equations each in accordance with a respective abstract data tree of which the `leaves` or extremities are signal values or constants. The parsing of each equation yields a respective partial truth table. The partial truth tables are merged to provide a complete truth table, which is preferably subjected to Boolean and/or expression optimization to reduce the number of entries in the truth table.
摘要翻译：生成电路单元库中的单元的真值表的计算机化方法包括以硬件描述语言表示单元的基本元素，将每个单元表示为该语言中的一组方程，并根据相应的抽象数据树，其“叶”或四肢是信号值或常数。每个方程的解析产生各自的部分真值表。将部分真值表合并以提供完整的真值表，其优选地经历布尔和/或表达式优化以减少真值表中的条目数。

7. 发明授权

US06233723B1 Circuit behavioral information analysis apparatus and a method of analyzing behavioral information of a circuit 失效
标题翻译：电路行为信息分析装置以及分析电路的行为信息的方法
公开(公告)号：US06233723B1
公开(公告)日：2001-05-15
申请号：US08919529
申请日：1997-08-28
申请人： Olivier Pribetich
发明人： Olivier Pribetich
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： The present invention provides stimuli generators, methods of analyzing a cell, methods of generating at least one stimuli, and methods of characterizing delay of a cell. One method of analyzing a cell in accordance with the invention includes providing a truth table which includes plural lines defining the logical behavior of a cell, the truth table comprising stimulus for application to the cell and output information generated by the cell responsive to applied stimulus; providing a preselected condition; and selectively extracting at least one stimuli from the truth table responsive to the preselected condition.
摘要翻译：本发明提供了刺激产生器，细胞分析方法，产生至少一种刺激的方法以及表征细胞延迟的方法。根据本发明的分析单元的一种方法包括提供真值表，其包括限定单元的逻辑行为的多个线，所述真值表包括用于应用于所述单元的激励并响应于所施加的刺激输出由所述单元产生的信息; 提供预选条件; 并且响应于预选条件从真值表中选择性地提取至少一个刺激。

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