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1. 发明申请

US20120094470A1 METHOD FOR FORMING INTEGRATED CIRCUITS ON A STRAINED SEMICONDUCTOR SUBSTRATE 有权
标题翻译：在应变半导体衬底上形成集成电路的方法
公开(公告)号：US20120094470A1
公开(公告)日：2012-04-19
申请号：US13240769
申请日：2011-09-22
申请人： Daniel Bensahel , Aomar Halimaoui
发明人： Daniel Bensahel , Aomar Halimaoui
IPC分类号： H01L21/762
CPC分类号： H01L29/7849 , H01L21/187 , H01L21/3063 , H01L29/06 , H01L29/32 , H01L29/78
摘要： A method for forming an electronic circuit on a strained semiconductor substrate, including the steps of: forming, on a first surface of a semiconductor substrate, electronic components defining electronic chips to be sawn; and forming at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.
摘要翻译：一种在应变半导体衬底上形成电子电路的方法，包括以下步骤：在半导体衬底的第一表面上形成限定要锯切的电子芯片的电子部件; 以及在所述半导体衬底的与所述第一表面相对的一侧的所述一侧上形成多孔半导体材料层的至少一部分以弯曲所述半导体衬底。

2. 发明授权

US07803694B2 Process for transferring a layer of strained semiconductor material 有权
标题翻译：用于转移应变半导体材料层的工艺
公开(公告)号：US07803694B2
公开(公告)日：2010-09-28
申请号：US12170583
申请日：2008-07-10
申请人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
发明人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L29/1054 , H01L21/76254 , H01L21/76259 , Y10S438/938
摘要： Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.
摘要翻译：半导体晶片具有应变半导体材料的薄层。这些结构包括底物; 基底上的氧化物层; 氧化物层上的碳化硅（SiC）层，以及在碳化硅层上处于应变状态的半导体材料的应变层，或者由施主衬底上的由随后的外延生长引起应变的材料制成的匹配层生长层; 在应变状态下具有规定厚度的半导体材料的应变层; 以及在应变层上的绝缘或半绝缘层，其厚度保持应变层的应变状态。绝缘层或半绝缘层由碳化硅或氧化物制成并用于将应变保留在应变层中。

3. 发明申请

US20070248818A1 Single-Crystal Semiconductor Layer with Heteroatomic Macronetwork 有权
标题翻译：单晶半导体层与杂原子大网络
公开(公告)号：US20070248818A1
公开(公告)日：2007-10-25
申请号：US10583235
申请日：2004-12-16
申请人： Daniel Bensahel , Yves Campidelli , Olivier Kermarrec
发明人： Daniel Bensahel , Yves Campidelli , Olivier Kermarrec
IPC分类号： B32B19/00
CPC分类号： H01L29/04 , B82Y10/00 , G02B1/02 , G02B5/18 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02513 , H01L21/02532 , H01L31/0352 , Y10T428/29
摘要： The invention relates to a single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism
摘要翻译：本发明涉及包括第二半导体材料的单晶纳米结构的第一半导体材料的单晶层，该纳米结构分布在具有中心的四边形棱镜的规则晶体网络中

4. 发明授权

US07279404B2 Process for fabricating strained layers of silicon or of a silicon/germanium alloy 有权
标题翻译：制造硅或硅/锗合金应变层的工艺
公开(公告)号：US07279404B2
公开(公告)日：2007-10-09
申请号：US10882995
申请日：2004-07-01
申请人： Aomar Halimaoui , Daniel Bensahel
发明人： Aomar Halimaoui , Daniel Bensahel
IPC分类号： H01L21/20
CPC分类号： H01L21/324 , H01L21/02381 , H01L21/0245 , H01L21/02513 , H01L21/02532 , H01L21/02694 , H01L29/7842 , Y10S438/96
摘要： A process for fabricating a strained layer of silicon or of a silicon/germanium alloy, includes:a) the formation of a layer (2) of silicon or of a silicon/germanium alloy on a layer (1) of a material having a modifiable lattice parameter; andb) the modification of the lattice parameter.
摘要翻译：一种制造硅或硅/锗合金应变层的工艺包括：a）在具有可修改的材料的层（1）上形成硅层或硅/锗合金层（2）晶格参数和b）修改晶格参数。

5. 发明授权

US06399502B1 Process for fabricating a planar heterostructure 失效
标题翻译：制造平面异质结构的方法
公开(公告)号：US06399502B1
公开(公告)日：2002-06-04
申请号：US09540188
申请日：2000-03-31
申请人： Caroline Hernandez , Yves Campidelli , Maurice Rivoire , Daniel Bensahel
发明人： Caroline Hernandez , Yves Campidelli , Maurice Rivoire , Daniel Bensahel
IPC分类号： H01L2100
CPC分类号： H01L31/1812 , B82Y10/00 , B82Y20/00 , H01L21/02381 , H01L21/0243 , H01L21/0245 , H01L21/02532 , H01L21/02664 , H01L21/32115 , H01L29/125 , H01L29/165 , H01L31/035254 , H01L33/24 , H01L33/34 , H01S5/0207 , H01S5/021 , H01S5/2234 , H01S5/3224 , Y02E10/50
摘要： The process comprises: etching, in a semiconductor substrate (2), at least one trench (3) with predetermined width and depth; depositing, on the substrate and in the trench, a stack of successive and alternate layers of Si1−xGex (0
摘要翻译：该方法包括：在半导体衬底（2）中蚀刻具有预定宽度和深度的至少一个沟槽（3）; 在衬底和沟槽中沉积Si1-xGex（0

6. 发明授权

US4678538A Process for the production of an insulating support on an oriented monocrystalline silicon film with localized defects 失效
标题翻译：在具有局部缺陷的取向单晶硅膜上生产绝缘支撑体的方法
公开(公告)号：US4678538A
公开(公告)日：1987-07-07
申请号：US853906
申请日：1986-04-21
申请人： Michel Haond , Daniel Bensahel , Didier Dutartre
发明人： Michel Haond , Daniel Bensahel , Didier Dutartre
IPC分类号： H01L21/20 , C30B13/34 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： C30B13/34
摘要： Process for the production of an oriented monocrystalline silicon film with localized defects on an insulating support.This process consists of covering a monocrystalline silicon support of orientation (100) with a SiO.sub.2 layer, producing in the latter a configuration having in the form of oriented (100) parallel insulating strips, an alternation of overhanging parts and recessed parts carrying out the etching of the SiO.sub.2 layer in order to locally form at the ends of said layer at least one opening, said etching being continued until the substrate is exposed, depositing on the etched SiO.sub.2 layer a silicon film, covering the silicon film with an encapsulating layer, carrying out a heat treatment of the structure obtained in order to recrystallize the silicon film in monocrystalline form with the same orientation as the substrate and eliminating the encapsulating layer.
摘要翻译：用于在绝缘支撑件上制造具有局部缺陷的取向单晶硅膜的方法。该方法包括用SiO 2层覆盖取向（100）的单晶硅支撑体，后者产生具有取向（100）平行绝缘条形式的构型，突出部分的交替和进行蚀刻的凹陷部分的SiO 2层，以在所述层的端部局部形成至少一个开口，所述蚀刻继续进行，直到基板被暴露，在蚀刻的SiO 2层上沉积硅膜，用封装层覆盖硅膜，承载对获得的结构进行热处理，以便以与衬底相同的取向以单晶形式重结晶硅膜并消除封装层。

7. 发明授权

US08049224B2 Process for transferring a layer of strained semiconductor material 有权
标题翻译：用于转移应变半导体材料层的工艺
公开(公告)号：US08049224B2
公开(公告)日：2011-11-01
申请号：US12862471
申请日：2010-08-24
申请人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
发明人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
IPC分类号： H01L29/12
CPC分类号： H01L29/1054 , H01L21/76254 , H01L21/76259 , Y10S438/938
摘要： Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.
摘要翻译：半导体晶片具有应变半导体材料的薄层。这些结构包括底物; 基底上的氧化物层; 氧化物层上的碳化硅（SiC）层，以及在碳化硅层上处于应变状态的半导体材料的应变层，或者由施主衬底上的由随后的外延生长引起应变的材料制成的匹配层生长层; 在应变状态下具有规定厚度的半导体材料的应变层; 以及在应变层上的绝缘或半绝缘层，其厚度保持应变层的应变状态。绝缘层或半绝缘层由碳化硅或氧化物制成并用于将应变保留在应变层中。

8. 发明申请

US20080164492A1 PROCESS FOR TRANSFERRING A LAYER OF STRAINED SEMICONDUCTOR MATERIAL 有权
标题翻译：用于传输应变半导体材料层的方法
公开(公告)号：US20080164492A1
公开(公告)日：2008-07-10
申请号：US12040134
申请日：2008-02-29
申请人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
发明人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
IPC分类号： H01L29/04 , H01L21/18
CPC分类号： H01L29/1054 , H01L21/76254 , H01L21/76259 , Y10S438/938
摘要： A process for preparing a semiconductor wafer with a strained layer having an elevated critical thickness. A first wafer having a strained layer of a semiconductor material on a matching layer is provided, with the semiconductor material having a first lattice parameter corresponding to a relaxed state and a first critical thickness corresponding to the first strained state, and the first thickness is less than the first critical thickness, The matching layer has a matching lattice parameter that is sufficiently different than the first lattice parameter to retain the strained layer in the strained state, The strained layer is transferred to a receiving substrate selected to provide the transferred strained layer with a second critical thickness that is greater than the first critical thickness, and additional semiconductor material is grown on the transferred strained layer to provide a second thickness that is greater than the first critical thickness and less than the second critical thickness, The invention also relates to the semiconductor structures that can be produced by the process.
摘要翻译：一种制备具有临界厚度升高的应变层的半导体晶片的方法。提供了在匹配层上具有半导体材料应变层的第一晶片，半导体材料具有对应于松弛状态的第一晶格参数和对应于第一应变状态的第一临界厚度，并且第一厚度较小匹配层具有与第一晶格参数充分不同的匹配晶格参数，以将应变层保持在应变状态。应变层被转移到选择的接收衬底以提供转移的应变层，第二临界厚度大于第一临界厚度，并且附加的半导体材料在转移的应变层上生长以提供大于第一临界厚度并小于第二临界厚度的第二厚度。本发明还涉及可以通过该方法生产的半导体结构。

9. 发明授权

US07129563B2 Method of fabricating a semiconductor device comprising a gate dielectric made of high dielectric permittivity material 有权
标题翻译：制造包括由高介电常数材料制成的栅极电介质的半导体器件的方法
公开(公告)号：US07129563B2
公开(公告)日：2006-10-31
申请号：US10815473
申请日：2004-04-01
申请人： Vincent Cosnier , Yves Morand , Olivier Kermarrec , Daniel Bensahel , Yves Campidelli
发明人： Vincent Cosnier , Yves Morand , Olivier Kermarrec , Daniel Bensahel , Yves Campidelli
IPC分类号： H01L31/0256
CPC分类号： H01L21/28185 , H01L21/2807 , H01L21/28194 , H01L29/4925 , H01L29/51 , H01L29/517
摘要： A process and a device for fabricating a semiconductor device having a gate dielectric made of high-k material, includes a step of depositing, directly on the gate dielectric, a first layer of Si1−xGex, where 0.5
摘要翻译：用于制造具有由高k材料制成的栅极电介质的半导体器件的工艺和器件包括直接在栅极电介质上沉积第一层Si 1-x Ge的步骤，在基本上低于通过热化学气相沉积（CVD）沉积多晶硅的温度的温度下，其中0.5

10. 发明授权

US06989570B2 Strained-channel isolated-gate field effect transistor, process for making same and resulting integrated circuit 有权
标题翻译：应变通道隔离栅场效应晶体管，制造相同的集成电路的过程
公开(公告)号：US06989570B2
公开(公告)日：2006-01-24
申请号：US10405075
申请日：2003-03-31
申请人： Thomas Skotnicki , Daniel Bensahel
发明人： Thomas Skotnicki , Daniel Bensahel
IPC分类号： H01L27/12
CPC分类号： H01L29/66651 , H01L29/0649 , H01L29/41783 , H01L29/66772 , H01L29/7842 , H01L29/78618 , H01L29/78639 , H01L29/78687
摘要： A transistor is located on a base layer 1 resting on a semiconductor substrate SB and formed from a relaxed silicon-germanium layer, and includes, under the isolated gate 7, a first strained silicon layer 2 resting on the base layer 1, surmounted by a buried insulating layer 10, surmounted by a second strained silicon layer 4 extending between the source S and drain D regions.
摘要翻译：晶体管位于沉积在半导体衬底SB上的基底层1上并由松弛的硅 - 锗层形成，并且在隔离栅极7下方包括搁置在基底层1上的第一应变硅层2，掩埋绝缘层10，其由在源极S和漏极D区域之间延伸的第二应变硅层4所覆盖。

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