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1. 发明申请

WO2007082227A3 MULTIPLE PORT MEMORY HAVING A PLURALITY OF PARALLEL CONNECTED TRENCH CAPACITORS IN A CELL 审中-公开
标题翻译：具有多个并联连接的电容器的多端口存储器
公开(公告)号：WO2007082227A3
公开(公告)日：2008-09-25
申请号：PCT/US2007060317
申请日：2007-01-10
申请人： IBM , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , MANDELMAN JACK A , RADENS CARL J , WANG GENG
发明人： CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , MANDELMAN JACK A , RADENS CARL J , WANG GENG
IPC分类号： G11C11/24 , H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： An integrated circuit is provided which includes a memory (100) having multiple ports per memory cell for accessing a data bit with each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plural of capacitors (102) connected together as a unitary source of capacitance (S). A first access transistor (104) is coupled between a firs one of the plurality of capacitors and a first bitline (RBL) and a second access transistor (106) is coupled between a second one of th plurality of capacitors and a second bitline (WBL) In each memory cell, a gate of the first access transistor (104) is connected to a fi wordline (RWL) and a gate of the second access transistor (106) is connected to a second wordline (WWL)
摘要翻译：提供一种集成电路，其包括每个存储器单元具有多个端口的存储器（100），用于利用多个存储器单元中的每一个访问数据位。这样的存储器包括存储单元阵列，其中每个存储单元包括连接在一起的多个电容器（102）作为电容（S）的整体源。第一存取晶体管（104）耦合在所述多个电容器中的第一个电容器中，并且第一位线（RBL）和第二存取晶体管（106）耦合在所述多个电容器中的第二电容器和第二位线（WBL ）在每个存储单元中，第一存取晶体管（104）的栅极连接到fi字线（RWL），第二存取晶体管（106）的栅极连接到第二字线（WWL）

2. 发明授权

US6278171B2 Sublithographic fuses using a phase shift mask 失效
标题翻译：使用相移掩模的亚光刻保险丝
公开(公告)号：US6278171B2
公开(公告)日：2001-08-21
申请号：US73466800
申请日：2000-12-13
申请人： IBM
发明人： ARNDT KENNETH C , HSU LOUIS L , MANDELMAN JACK A , MULLER K PAUL
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5258 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： A method for forming an interconnect wiring structure, such as a fuse structure, comprises forming an opening in an insulating layer using a phase shift mask (the opening having vertical sidewalls sloped sidewalls and horizontal surfaces), depositing a conductive material in the opening and removing the conductive material from the sloped sidewalls and horizontal surfaces, wherein the conductive material remains on the vertical sidewalls as fuse links.
摘要翻译：用于形成诸如熔丝结构的互连布线结构的方法包括使用相移掩模（具有垂直侧壁倾斜的侧壁和水平表面的开口）在绝缘层中形成开口，在开口中沉积导电材料并除去来自倾斜侧壁和水平表面的导电材料，其中导电材料作为熔丝链保持在垂直侧壁上。

3. 发明授权

US6444548B2 Bitline diffusion with halo for improved array threshold voltage control 失效
标题翻译：用光晕进行位线扩散，以改善阵列阈值电压控制
公开(公告)号：US6444548B2
公开(公告)日：2002-09-03
申请号：US25781799
申请日：1999-02-25
申请人： IBM
发明人： DIVAKARUNI RAMACHANDRA , LI YUJUN , MANDELMAN JACK A
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L21/8242 , H01L27/00 , H01L27/108 , H01L21/22 , H01L21/38 , H01L21/425 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10861 , H01L21/26586 , H01L27/10888 , H01L29/66492
摘要： A integrated circuit device and method for manufacturing an integrated circuit device includes forming a patterned gate stack, adjacent a storage device, to include a storage node diffusion region adjacent the storage device and a bitline contact diffusion region opposite the storage node diffusion region, implanting an impurity in the storage node diffusion region and the bitline contact diffusion region, forming an insulator layer over the patterned gate stack, removing a portion of the insulator layer from the bitline contact diffusion region to form sidewall spacers along a portion of the patterned gate stack adjacent the bitline contact diffusion region, implanting a halo implant into the bitline contact diffusion region, wherein the insulator layer is free from blocking the halo implant from the second diffusion region and annealing the integrated circuit device to drive the halo implant ahead of the impurity.
摘要翻译：一种用于制造集成电路器件的集成电路器件和方法，包括形成与存储器件相邻的图案化栅叠层，以包括与存储器件相邻的存储节点扩散区域和与存储节点扩散区域相对的位线接触扩散区域，在存储节点扩散区域和位线接触扩散区域中形成杂质，在图案化的栅极堆叠上形成绝缘体层，从位线接触扩散区域去除绝缘体层的一部分，以沿着图案化的栅极叠层的一部分相邻形成侧壁间隔物所述位线接触扩散区域将卤素注入物注入到所述位线接触扩散区域中，其中所述绝缘体层不从所述第二扩散区域阻挡所述卤素注入并退火所述集成电路器件以在所述杂质之前驱动所述卤素注入。

4. 发明公开

EP1977425A4 MULTIPLE PORT MEMORY HAVING A PLURALITY OF PARALLEL CONNECTED TRENCH CAPACITORS IN A CELL 审中-公开
标题翻译：多个并行电容器攫取更多的端口存储器在单元格中
公开(公告)号：EP1977425A4
公开(公告)日：2009-04-29
申请号：EP07710032
申请日：2007-01-10
申请人： IBM
发明人： CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , MANDELMAN JACK A , RADENS CARL J , WANG GENG
IPC分类号： G11C11/24 , H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors (102) connected together as a unitary source of capacitance. A first access transistor (104) is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor (106) is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.

5. 发明公开

EP0794567A3 Process for forming a deep trench-type storage node for a DRAM 失效
标题翻译：一种制备存储节点具有用于DRAM深度严重结构过程
公开(公告)号：EP0794567A3
公开(公告)日：2000-01-12
申请号：EP97102901
申请日：1997-02-21
申请人： SIEMENS AG , IBM
发明人： HO HERBERT L , SRINIVASAN RADHIKA , HALLE SCOTT D , HAMMERL ERWIN , DOBUZINSKY DAVID M , MANDELMAN JACK A , JASO MARK ANTHONY
IPC分类号： H01L27/04 , H01L21/02 , H01L21/762 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10861 , H01L21/76232 , H01L27/10832 , H01L28/82 , Y10S438/973
摘要： A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.

6. 发明公开

EP1565931A4 STRAINED FINFET CMOS DEVICE STRUCTURES 有权
标题翻译：权力结构对CMOS的FinFET设备
公开(公告)号：EP1565931A4
公开(公告)日：2006-04-19
申请号：EP02791319
申请日：2002-11-25
申请人： IBM
发明人： DORIS BRUCE B , CHIDAMBARRAO DURESETI , IEONG MEIKEI , MANDELMAN JACK A
IPC分类号： H01L21/00 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L27/12 , H01L29/786
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/823828 , H01L27/092 , H01L27/1203 , H01L29/66795 , H01L29/7842 , H01L29/7843
摘要： A semiconductor device structure, includes a PMOS device (200) and an NMOS device (300) disposed on a substrate (1, 2) the PMOS device including a compressive layer (6) stressing an active region of the PMOS device, the NMOS device including a tensile layer (9) stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices (200, 300).

7. 发明公开

EP0814507A1 Trench capacitor DRAM cell and method of making the same 失效
标题翻译： Grabenkondensator-Speicherzelle und Verfahren zur Herstellung derselben
公开(公告)号：EP0814507A1
公开(公告)日：1997-12-29
申请号：EP97304339
申请日：1997-06-20
申请人： SIEMENS AG , IBM
发明人： HAMMERL ERWIN , MANDELMAN JACK A , POSCHENRIEDER BERNHARD , SHORT ALVIN P , SRINIVASAN RADHIKA , STENGL REINHARD J , HO HERBERT L
IPC分类号： H01L27/00 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10832
摘要： Method for forming three-dimensional device structures such as a trench capacitor DRAM cell comprising a second device (370) formed over a first device (315) is disclosed. A layer (350,355) having a single crystalline top surface (350) is formed above the first device (315) to provide the base for forming the active area of the second device.
摘要翻译：公开了一种用于形成三维器件结构的方法，例如包括形成在第一器件（315）上的第二器件（370）的沟槽电容器DRAM单元。具有单晶顶表面（350）的层（350,355）形成在第一装置（315）上方，以提供用于形成第二装置的有效区域的基座。

8. 发明公开

EP1588403A4 LOW-GIDL MOSFET STRUCTURE AND METHOD FOR FABRICATION 有权
标题翻译：具有低GIDL和方法MOSFET结构
公开(公告)号：EP1588403A4
公开(公告)日：2010-03-24
申请号：EP04702490
申请日：2004-01-15
申请人： IBM
发明人： RADENS CARL , DOKUMACI OMER H , DORIS BRUCE B , GLUSCHENKOV OLEG , MANDELMAN JACK A
IPC分类号： H01L29/78 , H01L21/265 , H01L21/28 , H01L21/336 , H01L29/49
CPC分类号： H01L29/4983 , H01L21/26586 , H01L21/28105 , H01L29/66484 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7836 , Y10S257/90

9. 发明公开

EP1584108A4 HIGH PERFORMANCE EMBEDDED DRAM TECHNOLOGY WITH STRAINED SILICON 审中-公开
标题翻译：应变硅高性能的嵌入式DRAM技术
公开(公告)号：EP1584108A4
公开(公告)日：2006-06-07
申请号：EP03701269
申请日：2003-01-08
申请人： IBM
发明人： MANDELMAN JACK A , GAMBINO JEFFREY P , WANG GENG
IPC分类号： H01L21/20 , H01L21/308 , H01L21/8242
CPC分类号： H01L27/10894 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/3081 , H01L27/10864
摘要： Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device (66, 68, 70), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.

10. 发明公开

EP0720218A3 Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETS 失效
标题翻译：一种用于通过一个信道沟减少begrabenem具有有限在p-MOSFET的异常窄沟道效应的方法
公开(公告)号：EP0720218A3
公开(公告)日：1998-12-16
申请号：EP95119309
申请日：1995-12-07
申请人： SIEMENS AG , IBM
发明人： ALSMEIER JOHANN , MANDELMAN JACK A
IPC分类号： H01L21/8234 , H01L21/8242 , H01L29/78 , H01L21/76 , H01L29/10
CPC分类号： H01L27/10873 , H01L21/823412 , H01L29/7838
摘要： Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for significantly reducing the anomalous buried-channel p-MOSFET sensitivity to device width. In one embodiment, the method comprises the initiation of a low temperature annealing step using an inert gas after the deep phosphorous n-well implant step, and prior to the boron buried-channel implant and 850°C gate oxidation steps. Alternatively, the annealing step may be performed after the boron buried-channel implant and prior to the 850°C gate oxidation step. In another embodiment, a rapid thermal oxidation (RTO) step is substituted for the 850°C gate oxidation step, following the deep phosphorous n-well and boron buried-channel implant steps. Alternatively, an 850°C gate oxidation step may follow the RTO gate oxidation step.
摘要翻译：如动态随机存取存储器（DRAM）技术中，用于显着地减少到设备异常埋沟道p-MOSFET灵敏度制造沟槽界定埋沟p型金属氧化物半导体场效应晶体管（P-MOSFET）的，的方法宽度。在一个实施方式中，该方法包括深磷n阱注入步骤之后，使用惰性气体的低温退火步骤的开始，和硼埋沟道注入之前和850℃栅极氧化步骤。可替代地，退火步骤可以在硼埋沟植入物和850℃栅极氧化步骤之前，之后进行。在另一个实施方式快速热氧化（RTO）的步骤代替了850℃栅极氧化步骤，继深磷n阱和硼埋入沟道注入步骤。可替换地，在850℃下栅极氧化步骤可跟随RTO栅极氧化步骤。

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