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1. 发明申请

WO2007023011A2 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 审中-公开
标题翻译：双端口增益电池与侧面和顶部门控读取晶体管
公开(公告)号：WO2007023011A2
公开(公告)日：2007-03-01
申请号：PCT/EP2006063581
申请日：2006-06-27
申请人： IBM , IBM UK , MANDELMAN JACK , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , RADENS CARL , WANG GENG
发明人： MANDELMAN JACK , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , RADENS CARL , WANG GENG
IPC分类号： H01L27/108 , H01L21/8242 , H01L27/12
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储器单元和工艺序列。具体而言，本发明提供了与现有SOI CMOS技术兼容的密集，高性能SRAM单元替换。本领域已知各种增益单元布局。本发明通过提供用SOI CMOS制造的密集布局来改进现有技术。一般而言，存储器单元包括分别设置有栅极，源极和漏极的第一晶体管; 第二晶体管，分别具有第一栅极，第二栅极，源极和漏极; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

2. 发明申请

WO2007023011B1 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 审中-公开
标题翻译：双端口增益单元与侧面和顶部读取晶体管
公开(公告)号：WO2007023011B1
公开(公告)日：2007-07-12
申请号：PCT/EP2006063581
申请日：2006-06-27
申请人： IBM , IBM UK , MANDELMAN JACK , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , RADENS CARL , WANG GENG
发明人： MANDELMAN JACK , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , RADENS CARL , WANG GENG
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

3. 发明申请

WO2007082227A3 MULTIPLE PORT MEMORY HAVING A PLURALITY OF PARALLEL CONNECTED TRENCH CAPACITORS IN A CELL 审中-公开
标题翻译：具有多个并联连接的电容器的多端口存储器
公开(公告)号：WO2007082227A3
公开(公告)日：2008-09-25
申请号：PCT/US2007060317
申请日：2007-01-10
申请人： IBM , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , MANDELMAN JACK A , RADENS CARL J , WANG GENG
发明人： CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , MANDELMAN JACK A , RADENS CARL J , WANG GENG
IPC分类号： G11C11/24 , H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： An integrated circuit is provided which includes a memory (100) having multiple ports per memory cell for accessing a data bit with each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plural of capacitors (102) connected together as a unitary source of capacitance (S). A first access transistor (104) is coupled between a firs one of the plurality of capacitors and a first bitline (RBL) and a second access transistor (106) is coupled between a second one of th plurality of capacitors and a second bitline (WBL) In each memory cell, a gate of the first access transistor (104) is connected to a fi wordline (RWL) and a gate of the second access transistor (106) is connected to a second wordline (WWL)
摘要翻译：提供一种集成电路，其包括每个存储器单元具有多个端口的存储器（100），用于利用多个存储器单元中的每一个访问数据位。这样的存储器包括存储单元阵列，其中每个存储单元包括连接在一起的多个电容器（102）作为电容（S）的整体源。第一存取晶体管（104）耦合在所述多个电容器中的第一个电容器中，并且第一位线（RBL）和第二存取晶体管（106）耦合在所述多个电容器中的第二电容器和第二位线（WBL ）在每个存储单元中，第一存取晶体管（104）的栅极连接到fi字线（RWL），第二存取晶体管（106）的栅极连接到第二字线（WWL）

4. 发明申请

WO2007137946A3 TRENCH WIDENING WITHOUT MERGING 审中-公开
标题翻译：没有合并的TRENCH扩大
公开(公告)号：WO2007137946A3
公开(公告)日：2008-03-13
申请号：PCT/EP2007054769
申请日：2007-05-16
申请人： IBM , IBM UK , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA
发明人： CHENG KANGGUO , DIVAKARUNI RAMACHANDRA
IPC分类号： H01L29/94 , H01L21/334
CPC分类号： H01L29/945 , H01L29/66181
摘要： A semiconductor fabrication method comprises steps of providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench comprises a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110} side wall surfaces. The method further comprises the steps of removing portions of the blocking layer on the {110} side wall surfaces without removing portions of the blocking layer on the {100} side wall surfaces such that the {110} side wall surfaces are exposed to a surrounding ambient.
摘要翻译：半导体制造方法包括提供半导体结构的步骤。半导体结构包括半导体衬底，半导体衬底中的沟槽。沟槽包括侧壁，其包括{100}侧壁表面和{110}侧壁表面。半导体结构还包括在{100}侧壁表面和{110}侧壁表面上的阻挡层。该方法还包括以下步骤：除去{110}侧壁表面上的阻挡层的部分，而不去除{100}侧壁表面上的阻挡层的部分，使得{110}侧壁表面暴露于周围周围。

5. 发明申请

WO2007115002A3 SELF-ALIGNED BODY CONTACT FOR AN SEMICONDUCTOR-ON-INSULATOR TRENCH DEVICE AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：绝缘子半导体器件的自对准身体接触器及其制造方法
公开(公告)号：WO2007115002A3
公开(公告)日：2008-11-06
申请号：PCT/US2007064380
申请日：2007-03-20
申请人： IBM , DIVAKARUNI RAMACHANDRA , CHENG KANGGUO
发明人： DIVAKARUNI RAMACHANDRA , CHENG KANGGUO
IPC分类号： H01L21/44 , C01B32/50 , H01L21/00
CPC分类号： H01L29/7827 , H01L21/84 , H01L27/0207 , H01L27/10841 , H01L27/10876 , H01L29/66666 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of forming a body contact (215) for an semiconductor-on-insulator trench device. The method including: forming set of mandrels (190) on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers (195) on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening (197) in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench (200) in the substrate in the opening; and filling the contact trench with an electrically conductive material (210) to form the contact.
摘要翻译：一种形成用于绝缘体上半导体沟槽器件的体接触（215）的结构和方法。该方法包括：在基板的顶表面上形成一组心轴（190），该心轴组的每个心轴布置在多边形的不同角上并在衬底的顶表面上方延伸，一组心轴等于多边形的多个角; 在所述一组心轴的每个心轴的侧壁上形成侧壁间隔件（195），每个相邻的一对心轴的侧壁间隔件彼此合并并形成在多边形的内部区域中限定开口（197）的不间断的壁，区域的基板暴露在开口中; 蚀刻开口中的衬底中的接触沟槽（200）; 以及用导电材料（210）填充所述接触沟槽以形成所述接触。

6. 发明申请

WO2012106056A3 SELF-ALIGNED CONTACTS FOR HIGH K/METAL GATE PROCESS FLOW 审中-公开
标题翻译：高K /金属闸门工艺流程的自对准接触
公开(公告)号：WO2012106056A3
公开(公告)日：2012-10-18
申请号：PCT/US2012020020
申请日：2012-01-03
申请人： IBM , RAMACHANDRAN RAVIKUMAR , DIVAKARUNI RAMACHANDRA , LI YING
发明人： RAMACHANDRAN RAVIKUMAR , DIVAKARUNI RAMACHANDRA , LI YING
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L29/401 , H01L21/76895 , H01L21/76897 , H01L29/49 , H01L29/4983 , H01L29/51 , H01L29/66545 , H01L29/6656
摘要： A semiconductor structure is provided that includes a semiconductor substrate 12 having a plurality of gate stacks 14' located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer 42, a work function metal layer 44 and a conductive metal 46. A spacer 22 is located on sidewalls of each gate stack and a self- aligned dielectric liner 30 is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner 30 is present on an upper surface of a semiconductor metal alloy 28. A contact metal 34 is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner 30. The structure also includes another contact metal 60 having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed.
摘要翻译：提供半导体结构，其包括具有位于半导体衬底的表面上的多个栅极叠层14'的半导体衬底12。每个栅极堆叠从底部到顶部包括高k栅极电介质层42，功函数金属层44和导电金属46.间隔物22位于每个栅极堆叠的侧壁上，并且自对准电介质衬垫30是存在于每个间隔件的上表面上。每个自对准电介质衬垫30的底表面存在于半导体金属合金28的上表面上。接触金属34位于相邻的栅极叠层之间并且通过自对准电介质衬垫30与每个栅极叠层分开。该结构还包括另一接触金属60，其具有位于接触金属的上表面上并与其直接接触的部分以及位于栅叠层中的一个的导电金属上并与其直接接触的另一部分。还公开了使用替代栅极和非替代栅极方案形成半导体结构的方法。

7. 发明申请

WO03005447A8 STRUCTURE AND METHOD OF FABRICATING EMBEDDED VERTICAL DRAM ARRAYS WITH SILICIDED BITLINE AND POLYSILICON INTERCONNECT 审中-公开
标题翻译：嵌入式BITLINE和POLYSILICON INTERCONNECT嵌入垂直DRAM阵列的结构与方法
公开(公告)号：WO03005447A8
公开(公告)日：2004-02-19
申请号：PCT/GB0202961
申请日：2002-06-27
申请人： IBM , IBM UK , INFINEON TECHNOLOGIES AG
发明人： DIVAKARUNI RAMACHANDRA , GRUENING ULRIKE , MANDELMAN JACK , NESBIT LARRY , RADENS CARL
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/10876 , H01L27/10894
摘要： A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.
摘要翻译：用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域中制造具有硅化多晶硅层的垂直MOSFET DRAM单元，着陆焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠。该工艺消除了对M0金属化层的需要。

8. 发明申请

WO03005447A2 STRUCTURE AND METHOD OF FABRICATING EMBEDDED VERTICAL DRAM ARRAYS WITH SILICIDED BITLINE AND POLYSILICON INTERCONNECT 审中-公开
标题翻译：硅化双线和多晶硅互连嵌入式垂直DRAM阵列的结构和制作方法
公开(公告)号：WO03005447A2
公开(公告)日：2003-01-16
申请号：PCT/GB0202961
申请日：2002-06-27
申请人： IBM , IBM UK , INFINEON TECHNOLOGIES AG
发明人： DIVAKARUNI RAMACHANDRA , GRUENING ULRIKE , MANDELMAN JACK , NESBIT LARRY , RADENS CARL
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/10876 , H01L27/10894
摘要： A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.
摘要翻译：用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域，连接焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠中制造具有硅化多晶硅层的垂直MOSFET DRAM单元。该工艺消除了对M0金属化层的需求。

9. 发明授权

US6444548B2 Bitline diffusion with halo for improved array threshold voltage control 失效
标题翻译：用光晕进行位线扩散，以改善阵列阈值电压控制
公开(公告)号：US6444548B2
公开(公告)日：2002-09-03
申请号：US25781799
申请日：1999-02-25
申请人： IBM
发明人： DIVAKARUNI RAMACHANDRA , LI YUJUN , MANDELMAN JACK A
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L21/8242 , H01L27/00 , H01L27/108 , H01L21/22 , H01L21/38 , H01L21/425 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10861 , H01L21/26586 , H01L27/10888 , H01L29/66492
摘要： A integrated circuit device and method for manufacturing an integrated circuit device includes forming a patterned gate stack, adjacent a storage device, to include a storage node diffusion region adjacent the storage device and a bitline contact diffusion region opposite the storage node diffusion region, implanting an impurity in the storage node diffusion region and the bitline contact diffusion region, forming an insulator layer over the patterned gate stack, removing a portion of the insulator layer from the bitline contact diffusion region to form sidewall spacers along a portion of the patterned gate stack adjacent the bitline contact diffusion region, implanting a halo implant into the bitline contact diffusion region, wherein the insulator layer is free from blocking the halo implant from the second diffusion region and annealing the integrated circuit device to drive the halo implant ahead of the impurity.
摘要翻译：一种用于制造集成电路器件的集成电路器件和方法，包括形成与存储器件相邻的图案化栅叠层，以包括与存储器件相邻的存储节点扩散区域和与存储节点扩散区域相对的位线接触扩散区域，在存储节点扩散区域和位线接触扩散区域中形成杂质，在图案化的栅极堆叠上形成绝缘体层，从位线接触扩散区域去除绝缘体层的一部分，以沿着图案化的栅极叠层的一部分相邻形成侧壁间隔物所述位线接触扩散区域将卤素注入物注入到所述位线接触扩散区域中，其中所述绝缘体层不从所述第二扩散区域阻挡所述卤素注入并退火所述集成电路器件以在所述杂质之前驱动所述卤素注入。

10. 发明公开

EP2008300A4 SELF-ALIGNED BODY CONTACT FOR AN SEMICONDUCTOR-ON-INSULATOR TRENCH DEVICE AND METHOD OF FABRICATING SAME 有权
标题翻译：自对准身体接触，用于生产SOI抓斗成分及工艺
公开(公告)号：EP2008300A4
公开(公告)日：2012-05-23
申请号：EP07758889
申请日：2007-03-20
申请人： IBM
发明人： DIVAKARUNI RAMACHANDRA , CHENG KANGGUO
IPC分类号： H01L21/44 , C01B32/50 , H01L21/00 , H01L21/84 , H01L27/108 , H01L29/78
CPC分类号： H01L29/7827 , H01L21/84 , H01L27/0207 , H01L27/10841 , H01L27/10876 , H01L29/66666 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of forming a body contact for a semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench in the substrate in the opening; and filling the contact trench with an electrically conductive material to form the contact.

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