专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08044711B1 Clock signal noise shaping 有权
标题翻译：时钟信号噪声整形
公开(公告)号：US08044711B1
公开(公告)日：2011-10-25
申请号：US12704150
申请日：2010-02-11
申请人： Michael Yimin Zhang , Tat C. Choi
发明人： Michael Yimin Zhang , Tat C. Choi
IPC分类号： H03B1/00
CPC分类号： H03L7/16
摘要： A method and apparatus for clock signal noise shaping are described. Embodiments of a clock circuit include a filter coupled to receive an input clock signal and to provide an output clock signal. The filter filters noise of the input clock signal to shape the noise to provide the output clock signal. In a method for adjustment of phase noise, input clock signaling having the phase noise is obtained, and the input clock signal is filtered to adjust the phase noise to provide output clock signaling.
摘要翻译：描述了时钟信号噪声整形的方法和装置。时钟电路的实施例包括耦合以接收输入时钟信号并提供输出时钟信号的滤波器。滤波器滤除输入时钟信号的噪声，以形成噪声，以提供输出时钟信号。在调节相位噪声的方法中，获得具有相位噪声的输入时钟信号，并且对输入时钟信号进行滤波以调整相位噪声以提供输出时钟信号。

2. 发明授权

US5473342A Method and apparatus for on-the-fly multiple display mode switching in high-resolution bitmapped graphics system 失效
标题翻译：用于在高分辨率位图图形系统中实时多显示模式切换的方法和装置
公开(公告)号：US5473342A
公开(公告)日：1995-12-05
申请号：US138954
申请日：1993-10-19
申请人： Lawrence T. Tse , Tat C. Choi , David C. Soo
发明人： Lawrence T. Tse , Tat C. Choi , David C. Soo
IPC分类号： G09G5/02 , G09G5/06 , G09G5/36 , G09G5/39 , G09G5/395 , G09G1/02
CPC分类号： G09G5/02 , G09G5/06 , G09G5/39 , G09G5/395 , G09G2340/0407 , G09G2340/0435 , G09G5/363
摘要： A RAMDAC circuit drives a display device so as display multiple modes of color depth and display resolution in a single display frame without sacrificing resolution of the higher-resolution mode, and adjusts the output pixel rate to match that of the display mode being display on a pixel-by-pixel basis. The RAMDAC circuit switches between two graphics modes on-the-fly on a pixel-by-pixel basis in accordance with mode control bits stored in the pixel data. Furthermore, the RAMDAC circuit switches between two output pixel rates such that the amount of video memory used for any predefined screen area remains constant even though the output pixel rate and resolution are dynamically adjusted. In a preferred embodiment a display mode signal is embedded in the display data such that the display data, including the mode signal, comprises one byte of data for each display pixel when the mode signal specifies the first display mode, and comprises two bytes of data for each display pixel when the mode signal specifies the second display mode.
摘要翻译： RAMDAC电路驱动显示设备，以便在单个显示框架中显示多种颜色深度和显示分辨率的模式，而不会牺牲较高分辨率模式的分辨率，并且调整输出像素速率以匹配在显示模式下显示的显示模式逐个像素的基础。 RAMDAC电路根据存储在像素数据中的模式控制位在逐像素的基础上在两个图形模式之间切换。此外，RAMDAC电路在两个输出像素速率之间切换，使得即使输出像素速率和分辨率被动态地调整，用于任何预定屏幕区域的视频存储器的数量也保持恒定。在优选实施例中，显示模式信号被嵌入在显示数据中，使得当模式信号指定第一显示模式时，包括模式信号的显示数据包括每个显示像素的一个字节的数据，并且包括两个字节的数据对于每个显示像素，当模式信号指定第二显示模式时。

3. 发明授权

US4951112A Triple-poly 4T static ram cell with two independent transistor gates 失效
标题翻译：具有两个独立晶体管栅极的三聚四极静态柱塞电池
公开(公告)号：US4951112A
公开(公告)日：1990-08-21
申请号：US280782
申请日：1988-12-07
申请人： Tat C. Choi , Richard K. Klein , Craig S. Sander
发明人： Tat C. Choi , Richard K. Klein , Craig S. Sander
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , G11C11/412 , H01L27/1112 , Y10S257/904
摘要： A 4T static RAM cell (10) comprising a flip-flop with two pull-down transistors (18, 20) and two pass-gate transistors (12, 14) is fabaricated employing two separate gate oxide formations (74, 76) and associated separate polysilicon depositions (52a -b, 56). Two reduced area contacts (58, 60) connect to the nodes (26, 30) of the circuit (10). The reduced area butting contacts comprise vertically-disposed, doped polysilicon plugs (94), which intersect and electrically interconnect buried polysilicon layers (load poly 88, gate poly 52a) with doped silicon regions (80) in a bottom layer. Adding the processing steps of forming separate gate oxides for the pull-down and pass-gate transistors results in a smaller cell area and reduces the requirements of the contacts from three to two. Further, the separate gate oxidations permit independent optimization of the pull-down and pass-gate transistors.
摘要翻译：包括具有两个下拉晶体管（18,20）和两个通过栅晶体管（12,14）的触发器的4T静态RAM单元（10）通过采用两个单独的栅极氧化物层（74,76）和相关联的分离的多晶硅沉积物（52a-b，56）。两个缩小区域触点（58,60）连接到电路（10）的节点（26,30）。减小面积对接触点包括垂直布置的掺杂多晶硅插塞（94），其在底层中与埋入的多晶硅层（负载聚合物88，栅极聚合物52a）和掺杂的硅区域（80）电互连。为下拉和栅极晶体管添加形成单独的栅极氧化物的处理步骤导致更小的单元面积，并将触点的要求从三个减少到两个。此外，单独的栅极氧化允许下拉和栅极晶体管的独立优化。

4. 发明授权

US09030155B1 Multi-mode charger device 有权
标题翻译：多模充电器
公开(公告)号：US09030155B1
公开(公告)日：2015-05-12
申请号：US13540515
申请日：2012-07-02
申请人： Xianxin Li , Hong-Leong Hong , Adbullah Raouf , Anna Tam , John Chi-Hung Hui , Tat C. Choi
发明人： Xianxin Li , Hong-Leong Hong , Adbullah Raouf , Anna Tam , John Chi-Hung Hui , Tat C. Choi
IPC分类号： H02J7/00
CPC分类号： H02J7/0052 , G06F1/04 , G06F1/266 , H02J7/0003 , H02J2007/0001 , H02J2007/0062 , H02J2007/0096
摘要： Multi-mode charger device for charging portable devices and methods of charging portable devices are described. In an embodiment, a multi-mode charger device has mode blocks respectively associated with modes of operation which are coupled to a switch module. The switch module is for coupling a selected one of the mode blocks to a peripheral bus and to decouple the mode blocks remaining from the peripheral bus. A first mode of the modes of operation is a pass through mode. A second mode of the modes of operation is a first charging mode. A third mode of the modes of operation is a second charging mode. The first charging mode and the second charging mode are different from one another.
摘要翻译：描述用于对便携式设备进行充电的多模式充电器设备和便携式设备的充电方法。在一个实施例中，多模式充电器设备具有分别与耦合到开关模块的操作模式相关联的模式模块。开关模块用于将所选模式模块中的一个耦合到外设总线，并将剩余的模块与外围总线分离。操作模式的第一模式是通过模式。操作模式的第二模式是第一充电模式。操作模式的第三模式是第二充电模式。第一充电模式和第二充电模式彼此不同。

5. 发明授权

US08237414B1 Multi-mode charger device 有权
标题翻译：多模充电器
公开(公告)号：US08237414B1
公开(公告)日：2012-08-07
申请号：US12424081
申请日：2009-04-15
申请人： Xianxin Li , Hong-Leong Hong , Adbullah Raouf , Anna Tam , John Chi-Hung Hui , Tat C. Choi
发明人： Xianxin Li , Hong-Leong Hong , Adbullah Raouf , Anna Tam , John Chi-Hung Hui , Tat C. Choi
IPC分类号： H02J7/00
CPC分类号： H02J7/0052 , G06F1/04 , G06F1/266 , H02J7/0003 , H02J2007/0001 , H02J2007/0062 , H02J2007/0096
摘要： Multi-mode charger device for charging portable devices and methods of charging portable devices are described. In an embodiment, a multi-mode charger device has mode blocks respectively associated with modes of operation which are coupled to a switch module. The switch module is for coupling a selected one of the mode blocks to a peripheral bus and to decouple the mode blocks remaining from the peripheral bus. A first mode of the modes of operation is a pass through mode. A second mode of the modes of operation is a first charging mode. A third mode of the modes of operation is a second charging mode. The first charging mode and the second charging mode are different from one another.
摘要翻译：描述用于对便携式设备进行充电的多模式充电器设备和便携式设备的充电方法。在一个实施例中，多模式充电器设备具有分别与耦合到开关模块的操作模式相关联的模式模块。开关模块用于将所选模式模块中的一个耦合到外设总线，并将剩余的模块与外围总线分离。操作模式的第一模式是通过模式。操作模式的第二模式是第一充电模式。操作模式的第三模式是第二充电模式。第一充电模式和第二充电模式彼此不同。

6. 发明授权

US4912540A Reduced area butting contact structure 失效
标题翻译：减少对接接触结构
公开(公告)号：US4912540A
公开(公告)日：1990-03-27
申请号：US230696
申请日：1988-08-05
申请人： Craig S. Sander , Richard K. Klein , Tat C. Choi
发明人： Craig S. Sander , Richard K. Klein , Tat C. Choi
IPC分类号： H01L21/768 , H01L29/04 , H01L23/48 , H01L29/34
CPC分类号： H01L21/76895 , H01L21/7684 , H01L21/76877
摘要： A reduced area butting contact structure (10') is provided, which is especially suited for four-transistor static RAM cells. A structure is formed which includes a doped silicon region and one or more layers of polysilicon and oxide situated thereabove, one of which layers of polysilicon may be a gate polysilicon. An anisotropic etch is then performed through all upper layers including any upper polysilicon layers which may be present, but stopping at the doped silicon region and any gate polysilicon layers present, to form a contact hole (26'). The contact hole is filled with a conductive plug (32) of a material such as tungsten or polysilicon and etched back. In either case, contact with all polysilicon layers present and the doped silicon region is made. In the anisotropic etching process, a two-step etch is employed. The first etch is non-specific as to material, etching all relevant materials (polysilicon and oxide) at substantially the same rate and is continued through any upper polysilicon layers, but is terminated prior to etching the doped silicon region or any gate polysilicon layers (22). The second etch is specific as to material, etching silicon dioxide faster than polysilicon or silicon, and thus stops at the gate polysilicon layer and the doped silicon region.
摘要翻译：提供了减小面积对接接触结构（10'），其特别适用于四晶体管静态RAM单元。形成了包括掺杂硅区域和位于其上方的一层或多层多晶硅和氧化物的结构，其中一层多晶硅可以是栅极多晶硅。然后通过所有上层进行各向异性蚀刻，所述上层包括可能存在的任何上多晶硅层，但在掺杂硅区域和存在的任何栅多晶硅层停止以形成接触孔（26'）。接触孔填充有诸如钨或多晶硅的材料的导电插塞（32）并被回蚀。在任一种情况下，与存在的所有多晶硅层和掺杂的硅区域接触。在各向异性蚀刻工艺中，采用两步蚀刻。第一蚀刻对于材料是非特异性的，以基本上相同的速率蚀刻所有相关材料（多晶硅和氧化物）并且继续通过任何上多晶硅层，但是在蚀刻掺杂硅区域或任何栅极多晶硅层之前终止 22）。第二蚀刻对于材料是特定的，比多晶硅或硅更快地蚀刻二氧化硅，因此停止在栅极多晶硅层和掺杂的硅区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式