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1. 发明授权

US09768255B2 Semiconductor devices including contact structures that partially overlap silicide layers 有权
公开(公告)号：US09768255B2
公开(公告)日：2017-09-19
申请号：US15006717
申请日：2016-01-26
申请人： Do-Sun Lee , Chang-Woo Sohn , Chul-Sung Kim , Shigenobu Maeda , Young-Moon Choi , Hyo-Seok Choi , Sang-Jin Hyun
发明人： Do-Sun Lee , Chang-Woo Sohn , Chul-Sung Kim , Shigenobu Maeda , Young-Moon Choi , Hyo-Seok Choi , Sang-Jin Hyun
IPC分类号： H01L29/08 , H01L29/06 , H01L29/161 , H01L29/165 , H01L29/78 , H01L29/417
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/161 , H01L29/165 , H01L29/41791 , H01L29/7848 , H01L29/785
摘要： Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.

2. 发明申请

US20160308004A1 SEMICONDUCTOR DEVICES INCLUDING CONTACT STRUCTURES THAT PARTIALLY OVERLAP SILICIDE LAYERS 有权
标题翻译：半导体器件，包括部分覆盖硅化物层的接触结构
公开(公告)号：US20160308004A1
公开(公告)日：2016-10-20
申请号：US15006717
申请日：2016-01-26
申请人： Do-Sun LEE , Chang-Woo SOHN , Chul-Sung KIM , Shigenobu MAEDA , Young-Moon CHOI , Hyo-Seok CHOI , Sang-Jin HYUN
发明人： Do-Sun LEE , Chang-Woo SOHN , Chul-Sung KIM , Shigenobu MAEDA , Young-Moon CHOI , Hyo-Seok CHOI , Sang-Jin HYUN
IPC分类号： H01L29/08 , H01L29/165 , H01L29/161 , H01L29/78 , H01L29/06
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/161 , H01L29/165 , H01L29/41791 , H01L29/7848 , H01L29/785
摘要： Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.
摘要翻译：提供半导体器件。半导体器件包括衬底。半导体器件包括限定基板的有效部分的隔离层，其在一个方向上彼此间隔开。半导体器件在有源部分上包括外延层。半导体器件在外延层上包括金属硅化物层。此外，半导体器件包括仅在外延层上部分地重叠金属硅化物层的接触结构。还提供了形成半导体器件的相关方法。

3. 发明授权

US08530303B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08530303B2
公开(公告)日：2013-09-10
申请号：US13243147
申请日：2011-09-23
申请人： Jin-Bum Kim , Chul-Sung Kim , Yu-Gyun Shin , Dae-Yong Kim , Joon-Gon Lee , Kwang-Young Lee
发明人： Jin-Bum Kim , Chul-Sung Kim , Yu-Gyun Shin , Dae-Yong Kim , Joon-Gon Lee , Kwang-Young Lee
IPC分类号： H01L21/8249
CPC分类号： H01L21/823807 , H01L21/823814
摘要： A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.
摘要翻译：制造半导体的方法包括提供具有限定在其中的第一区域和第二区域的衬底，在第一区域中形成第一栅极和第一源极和漏极区域，并在第一区域中形成第二栅极和第二源极和漏极区域在所述第二源极和漏极区域中形成外延层，在所述第一源极和漏极区域中形成第一金属硅化物层，在所述第一区域和所述第二区域上形成层间电介质层，形成多个接触孔，第一金属硅化物层和外延层，同时穿透层间电介质层，在暴露的外延层中形成第二金属硅化物层，并且通过填充多个接触孔形成与第一和第二金属硅化物层接触的多个触点。

4. 发明授权

US08481387B2 Method of forming an insulation structure and method of manufacturing a semiconductor device using the same 有权
标题翻译：绝缘结构的形成方法及其制造方法
公开(公告)号：US08481387B2
公开(公告)日：2013-07-09
申请号：US13188587
申请日：2011-07-22
申请人： Jung-Geun Jee , Young-Jin Noh , Bon-Young Koo , Chul-Sung Kim , Hun-Hyeoung Leam , Woong Lee
发明人： Jung-Geun Jee , Young-Jin Noh , Bon-Young Koo , Chul-Sung Kim , Hun-Hyeoung Leam , Woong Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/3144 , H01L21/0217 , H01L21/022 , H01L21/02238 , H01L21/02252 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/31662 , H01L27/115 , H01L27/11521
摘要： In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure may have a thickness substantially the same as that of a central portion of the insulation structure so that the insulation structure may have a uniform thickness and improved insulation characteristics. When the insulation structure is employed as a tunnel insulation layer of a semiconductor device, the semiconductor device may have enhanced endurance and improved electrical characteristics because a threshold voltage distribution of cells in the semiconductor device may become uniform.
摘要翻译：在形成绝缘结构的方法中，通过至少一个氧化工艺在物体上形成至少一个氧化物层，然后通过至少一个硝化工艺从氧化物层形成至少一个氮化物层。绝缘结构的边缘部分可以具有与绝缘结构的中心部分的厚度基本相同的厚度，使得绝缘结构可以具有均匀的厚度和改善的绝缘特性。当采用绝缘结构作为半导体器件的隧道绝缘层时，由于半导体器件中的单元的阈值电压分布可能变得均匀，所以半导体器件可以具有增强的耐久性和改善的电特性。

5. 发明申请

US20130121111A1 Method Of Generating and Combining Multiple Horizons To Determine A Seismic Horizon And Its Uncertainty 审中-公开
标题翻译：生成和组合多个视野以确定地震地平线及其不确定性的方法
公开(公告)号：US20130121111A1
公开(公告)日：2013-05-16
申请号：US13651204
申请日：2012-10-12
申请人： Chul-Sung Kim , Mark W. Dobin
发明人： Chul-Sung Kim , Mark W. Dobin
IPC分类号： G01V1/28
CPC分类号： G01V1/301 , G01V2210/643
摘要： There is provided a system and method for creating model of a subsurface region based on multiple depth values. The method includes selecting seeds that represent a starting location within a desired horizon surfaces and generating a plurality of candidate horizons from the selected seeds. A number of depth values from the candidate horizons may be combined into a representative depth value and an uncertainty may be computed based on discrepancies among the depth values. A model of the subsurface region may be created using the depth values and the uncertainty.
摘要翻译：提供了一种基于多个深度值来创建地下区域模型的系统和方法。该方法包括选择表示期望的水平表面内的开始位置的种子，并从所选择的种子生成多个候选水平面。来自候选视野的多个深度值可以被组合成代表性的深度值，并且可以基于深度值之间的差异来计算不确定性。可以使用深度值和不确定性来创建地下区域的模型。

6. 发明授权

US08008214B2 Method of forming an insulation structure and method of manufacturing a semiconductor device using the same 有权
标题翻译：绝缘结构的形成方法及其制造方法
公开(公告)号：US08008214B2
公开(公告)日：2011-08-30
申请号：US11639164
申请日：2006-12-15
申请人： Jung-Geun Jee , Young-Jin Noh , Bon-Young Koo , Chul-Sung Kim , Hun-Hyeoung Leam , Woong Lee
发明人： Jung-Geun Jee , Young-Jin Noh , Bon-Young Koo , Chul-Sung Kim , Hun-Hyeoung Leam , Woong Lee
IPC分类号： H01L21/31 , H01L21/461
CPC分类号： H01L21/3144 , H01L21/0217 , H01L21/022 , H01L21/02238 , H01L21/02252 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/31662 , H01L27/115 , H01L27/11521
摘要： In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure may have a thickness substantially the same as that of a central portion of the insulation structure so that the insulation structure may have a uniform thickness and improved insulation characteristics. When the insulation structure is employed as a tunnel insulation layer of a semiconductor device, the semiconductor device may have enhanced endurance and improved electrical characteristics because a threshold voltage distribution of cells in the semiconductor device may become uniform.
摘要翻译：在形成绝缘结构的方法中，通过至少一个氧化工艺在物体上形成至少一个氧化物层，然后通过至少一个硝化工艺从氧化物层形成至少一个氮化物层。绝缘结构的边缘部分可以具有与绝缘结构的中心部分的厚度基本相同的厚度，使得绝缘结构可以具有均匀的厚度和改善的绝缘特性。当采用绝缘结构作为半导体器件的隧道绝缘层时，由于半导体器件中的单元的阈值电压分布可能变得均匀，所以半导体器件可以具有增强的耐久性和改善的电特性。

7. 发明授权

US07893482B2 Semiconductor devices having tunnel and gate insulating layers 失效
标题翻译：具有隧道和栅极绝缘层的半导体器件
公开(公告)号：US07893482B2
公开(公告)日：2011-02-22
申请号：US12428078
申请日：2009-04-22
申请人： Chul-sung Kim , Young-jin Noh , Bon-young Koo , Sung-kweon Baek
发明人： Chul-sung Kim , Young-jin Noh , Bon-young Koo , Sung-kweon Baek
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A semiconductor device includes a semiconductor substrate having a surface, buried isolation regions protruding from the surface of the semiconductor substrate, and a first insulating layer on the surface of the semiconductor substrate between the isolation regions and including a fluorine, nitrogen, and/or heavy hydrogen impurity. A floating electrode is on the first insulating layer, a second insulating layer is on the floating electrode and the isolation regions, and a control gate electrode is on the second insulating layer. Related methods of forming semiconductor devices are also disclosed.
摘要翻译：半导体器件包括具有表面的半导体衬底，从半导体衬底的表面突出的掩埋隔离区域和在隔离区域之间的半导体衬底的表面上的第一绝缘层，并且包括氟，氮和/或重的氢杂质。浮置电极位于第一绝缘层上，第二绝缘层位于浮置电极和隔离区上，而控制栅极位于第二绝缘层上。还公开了形成半导体器件的相关方法。

8. 发明授权

US07692196B2 Memory devices and methods of manufacturing the same 失效
标题翻译：存储器件及其制造方法
公开(公告)号：US07692196B2
公开(公告)日：2010-04-06
申请号：US11655689
申请日：2007-01-19
申请人： In-Sang Jeon , Sang-Bom Kang , Dong-Chan Kim , Chul-Sung Kim , Sug-Hun Hong , Sang-Jin Hyun
发明人： In-Sang Jeon , Sang-Bom Kang , Dong-Chan Kim , Chul-Sung Kim , Sug-Hun Hong , Sang-Jin Hyun
IPC分类号： H01L27/108
CPC分类号： H01L21/28282 , H01L29/513 , H01L29/792 , Y10S257/908
摘要： The memory device includes a first tunnel insulation layer pattern on a semiconductor substrate, a second tunnel insulation layer pattern having an energy band gap lower than that of the first tunnel insulation layer pattern on the first tunnel insulation layer pattern, a charge trapping layer pattern on the second tunnel insulation layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode on the blocking layer pattern. The memory device further includes a source/drain region at an upper portion of the semiconductor substrate. The upper portion of the semiconductor substrate is adjacent to the first tunnel insulation layer pattern.
摘要翻译：存储器件包括在半导体衬底上的第一隧道绝缘层图案，第二隧道绝缘层图案，其第一隧道绝缘层图案上具有比第一隧道绝缘层图案低的能带隙，第二隧道绝缘层图案，电荷俘获层图案上的阻挡层图案，以及阻挡层图案上的栅电极。存储器件还包括在半导体衬底的上部的源极/漏极区域。半导体衬底的上部与第一隧道绝缘层图案相邻。

9. 发明授权

US07511340B2 Semiconductor devices having gate structures and contact pads that are lower than the gate structures 失效
标题翻译：具有栅极结构的半导体器件和低于栅极结构的接触焊盘
公开(公告)号：US07511340B2
公开(公告)日：2009-03-31
申请号：US11779477
申请日：2007-07-18
申请人： Deok-Hyung Lee , Si-Young Choi , Byeong-Chan Lee , Chul-Sung Kim , In-Soo Jung , Jong-Ryeol Yoo
发明人： Deok-Hyung Lee , Si-Young Choi , Byeong-Chan Lee , Chul-Sung Kim , In-Soo Jung , Jong-Ryeol Yoo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10888 , H01L21/28525 , H01L21/76829 , H01L21/76832 , H01L21/76895 , H01L23/485 , H01L27/10894 , H01L2924/0002 , Y10S257/90 , H01L2924/00
摘要： Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and on exposed sidewalls of the first contact pads. Second contact pads are disposed on the first contact pads.
摘要翻译：半导体器件在半导体衬底上具有栅极结构，在相应栅极结构的侧壁上具有第一间隔物。第一接触垫位于栅极结构之间并且具有低于栅极结构的高度的高度。第二间隔件设置在第一间隔件的侧壁和第一接触垫的暴露的侧壁上。第二接触垫设置在第一接触垫上。

10. 发明申请

US20090020805A1 NON-VOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20090020805A1
公开(公告)日：2009-01-22
申请号：US11950143
申请日：2007-12-04
申请人： Jin-Hwa Heo , Chul-Sung Kim , Bon-Young Koo , Ki-Hyun Hwang , Chang-Hyun Lee
发明人： Jin-Hwa Heo , Chul-Sung Kim , Bon-Young Koo , Ki-Hyun Hwang , Chang-Hyun Lee
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L21/28202 , H01L29/40117 , H01L29/4234 , H01L29/513 , H01L29/518
摘要： A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.
摘要翻译：非易失性存储器件包括电荷存储层和衬底之间的电介质层。可以减少电介质层的自由键，以减少/防止电荷通过游离键泄漏和/或被游离键捕获。结果，可以增强非挥发性存储器件的数据保持性能和/或耐久性。

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