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1. 发明授权

US08669641B2 Diffusion region routing for narrow scribe-line devices 有权
标题翻译：窄划线设备的扩散区域路由
公开(公告)号：US08669641B2
公开(公告)日：2014-03-11
申请号：US13164523
申请日：2011-06-20
申请人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
发明人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
IPC分类号： H01L21/78
CPC分类号： H01L23/585 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
摘要翻译：本公开提供了一种制造集成电路（IC）装置的方法。该方法包括在半导体衬底中形成第一IC特征和第二IC特征，第一和第二IC特征彼此间隔开并由划线区分开; 在所述半导体衬底中至少部分地在所述划线区域内形成掺杂的布线特征并且被配置为连接所述第一和第二IC特征; 在所述半导体衬底上形成多层互连（MLI）结构和层间电介质（ILD），其中所述MLI被配置为在所述划线区域内不存在; 并且在刻划区域内蚀刻ILD和半导体衬底以形成划线沟槽。

2. 发明申请

US20100013059A1 DIFFUSION REGION ROUTING FOR NARROW SCRIBE-LINE DEVICES 有权
标题翻译：用于NARROW SCRIBE-LINE设备的扩展区域路由
公开(公告)号：US20100013059A1
公开(公告)日：2010-01-21
申请号：US12173121
申请日：2008-07-15
申请人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
发明人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
IPC分类号： H01L21/302 , H01L23/544
CPC分类号： H01L23/585 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
摘要翻译：本公开提供了一种制造集成电路（IC）装置的方法。该方法包括在半导体衬底中形成第一IC特征和第二IC特征，第一和第二IC特征彼此间隔开并由划线区分开; 在所述半导体衬底中至少部分地在所述划线区域内形成掺杂的布线特征并且被配置为连接所述第一和第二IC特征; 在所述半导体衬底上形成多层互连（MLI）结构和层间电介质（ILD），其中所述MLI被配置为在所述划线区域内不存在; 并且在刻划区域内蚀刻ILD和半导体衬底以形成划线沟槽。

3. 发明申请

US20080061343A1 Metal-oxide-metal structure with improved capacitive coupling area 审中-公开
标题翻译：具有改善电容耦合面积的金属氧化物 - 金属结构
公开(公告)号：US20080061343A1
公开(公告)日：2008-03-13
申请号：US11518470
申请日：2006-09-08
申请人： Chin Kun Lan , Sheng-Wen Chen , Hung Jui Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Chin Kun Lan , Sheng-Wen Chen , Hung Jui Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L29/94
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A stacked metal-oxide-metal (MOM) capacitor structure and method of forming the same to increase an electrode/capacitor dielectric coupling area to increase a capacitance, the MOM capacitor structure including a plurality of metallization layers in stacked relationship; wherein each metallization layer includes substantially parallel spaced apart conductive electrode line portions having a first intervening capacitor dielectric; and, wherein the conductive electrode line portions are electrically interconnected between metallization layers by conductive damascene line portions formed in a second capacitor dielectric and disposed underlying the conductive electrode line portions.
摘要翻译：一种堆叠的金属氧化物金属（MOM）电容器结构及其形成方法，以增加电极/电容器介质耦合面积以增加电容，所述MOM电容器结构包括堆叠关系的多个金属化层; 其中每个金属化层包括具有第一中间电容器电介质的基本上平行的隔开的导电电极线部分; 并且其中所述导电电极线部分通过形成在第二电容器电介质中并设置在所述导电电极线部分下方的导电镶嵌线部分在金属化层之间电互连。

4. 发明申请

US20110241179A1 DIFFUSION REGION ROUTING FOR NARROW SCRIBE-LINE DEVICES 有权
标题翻译：用于NARROW SCRIBE-LINE设备的扩展区域路由
公开(公告)号：US20110241179A1
公开(公告)日：2011-10-06
申请号：US13164523
申请日：2011-06-20
申请人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
发明人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
IPC分类号： H01L23/544
CPC分类号： H01L23/585 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
摘要翻译：本公开提供了一种制造集成电路（IC）装置的方法。该方法包括在半导体衬底中形成第一IC特征和第二IC特征，第一和第二IC特征彼此间隔开并由划线区分开; 在所述半导体衬底中至少部分地在所述划线区域内形成掺杂的布线特征并且被配置为连接所述第一和第二IC特征; 在所述半导体衬底上形成多层互连（MLI）结构和层间电介质（ILD），其中所述MLI被配置为在所述划线区域内不存在; 并且在刻划区域内蚀刻ILD和半导体衬底以形成划线沟槽。

5. 发明授权

US07968431B2 Diffusion region routing for narrow scribe-line devices 有权
标题翻译：窄划线设备的扩散区域路由
公开(公告)号：US07968431B2
公开(公告)日：2011-06-28
申请号：US12173121
申请日：2008-07-15
申请人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
发明人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
IPC分类号： H01L23/544
CPC分类号： H01L23/585 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
摘要翻译：本公开提供了一种制造集成电路（IC）装置的方法。该方法包括在半导体衬底中形成第一IC特征和第二IC特征，第一和第二IC特征彼此间隔开并由划线区分开; 在所述半导体衬底中至少部分地在所述划线区域内形成掺杂的布线特征并且被配置为连接所述第一和第二IC特征; 在所述半导体衬底上形成多层互连（MLI）结构和层间电介质（ILD），其中所述MLI被配置为在所述划线区域内不存在; 并且在刻划区域内蚀刻ILD和半导体衬底以形成划线沟槽。

6. 发明授权

US07955993B2 Oxygen plasma reduction to eliminate precursor overflow in BPTEOS film deposition 有权
标题翻译：氧气等离子体还原以消除BPTEOS薄膜沉积中的前体溢出
公开(公告)号：US07955993B2
公开(公告)日：2011-06-07
申请号：US12478493
申请日：2009-06-04
申请人： Chin Kun Lan , Sheng-Wen Chen , Hung Jui Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Chin Kun Lan , Sheng-Wen Chen , Hung Jui Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31625 , H01L21/02129 , H01L21/02271 , H01L21/0234 , H01L21/3105 , H01L21/76826
摘要： A method including providing a semiconductor substrate in a reaction chamber; flowing a first reactant including silicon and oxygen, a boron dopant and a phosphorus dopant into the reaction chamber so that a layer of BPTEOS is deposited on the semiconductor substrate; stopping the flow of the first reactant, boron dopant and phosphorus dopant into the reaction chamber and so that a phosphorus dopant and boron dopant rich film is deposited over the layer of BPTEOS; and reducing the film comprising exposing the film to an O2 plasma.
摘要翻译：一种包括在反应室中提供半导体衬底的方法; 将包括硅和氧的第一反应物，硼掺杂剂和磷掺杂剂流动到反应室中，使得在半导体衬底上沉积BPTEOS层; 阻止第一反应物，硼掺杂剂和磷掺杂剂流入反应室，使得磷掺杂剂和硼掺杂剂富含膜沉积在BPTEOS层上; 并且还原膜包括将膜暴露于O 2等离子体。

7. 发明申请

US20100311252A1 OXYGEN PLASMA REDUCTION TO ELIMINATE PRECURSOR OVERFLOW IN BPTEOS FILM DEPOSITION 有权
标题翻译：消除BPTEOS膜沉积中前体溢出的氧气等离子体减少
公开(公告)号：US20100311252A1
公开(公告)日：2010-12-09
申请号：US12478493
申请日：2009-06-04
申请人： Chin Kun Lan , Sheng-Wen Chen , Hung Jui Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Chin Kun Lan , Sheng-Wen Chen , Hung Jui Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/283 , H01L21/285
CPC分类号： H01L21/31625 , H01L21/02129 , H01L21/02271 , H01L21/0234 , H01L21/3105 , H01L21/76826
摘要： A method including providing a semiconductor substrate in a reaction chamber; flowing a first reactant including silicon and oxygen, a boron dopant and a phosphorus dopant into the reaction chamber so that a layer of BPTEOS is deposited on the semiconductor substrate; stopping the flow of the first reactant, boron dopant and phosphorus dopant into the reaction chamber and so that a phosphorus dopant and boron dopant rich film is deposited over the layer of BPTEOS; and reducing the film comprising exposing the film to an O2 plasma.
摘要翻译：一种包括在反应室中提供半导体衬底的方法; 将包括硅和氧的第一反应物，硼掺杂剂和磷掺杂剂流动到反应室中，使得在半导体衬底上沉积BPTEOS层; 阻止第一反应物，硼掺杂剂和磷掺杂剂流入反应室，使得磷掺杂剂和富含硼的掺杂剂的膜沉积在BPTEOS层上; 并且还原膜包括将膜暴露于O 2等离子体。

8. 发明授权

US06645825B1 Planarization of shallow trench isolation (STI) 有权
标题翻译：浅沟槽隔离（STI）的平面化
公开(公告)号：US06645825B1
公开(公告)日：2003-11-11
申请号：US09614554
申请日：2000-07-12
申请人： Chin Kun Lan , Ting Chun Wang , Tong-Hua Kuan , Ying-Lang Wang
发明人： Chin Kun Lan , Ting Chun Wang , Tong-Hua Kuan , Ying-Lang Wang
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： An improved and new process for fabricating a planarized structure of shallow trench isolation (STI) embedded in a silicon substrate has been developed. The planarizing method comprises a two-step CMP process in which the first CMP step comprises chemical-mechanical polishing of silicon oxide using a first polishing slurry which is selective to silicon oxide. The time of the second CMP step is determined by selecting an overpolish thickness based on the percentage of substrate area occupied by the trench. High manufacturing yield and superior planarity for silicon oxide STI are achieved.
摘要翻译：已经开发了一种用于制造嵌入硅衬底中的浅沟槽隔离（STI）的平面化结构的改进和新工艺。平面化方法包括两步CMP工艺，其中第一CMP步骤包括使用对氧化硅选择性的第一抛光浆料进行二氧化硅的化学机械抛光。通过基于沟槽占据的衬底面积的百分比来选择过抛光厚度来确定第二CMP步骤的时间。实现了高的制造成品率和优异的氧化硅STI平坦度。

9. 发明授权

US06407007B1 Method to solve the delamination of a silicon nitride layer from an underlying spin on glass layer 有权
标题翻译：解决氮化硅层从玻璃层上的底层旋转分层的方法
公开(公告)号：US06407007B1
公开(公告)日：2002-06-18
申请号：US09193669
申请日：1998-11-17
申请人： Chun-Ching Tsan , Ying-Lang Wang , Hui-Ling Wang , Chin Kun Lan
发明人： Chun-Ching Tsan , Ying-Lang Wang , Hui-Ling Wang , Chin Kun Lan
IPC分类号： H01L21324
CPC分类号： H01L21/3185 , H01L21/316 , H01L21/76826
摘要： A method for improving the adhesion of a thick silicon nitride layer, to an underlying spin on glass, (SOG), layer, has been developed. After applying, baking and curing of a SOG layer, plasma treatment of the SOG layer, is performed in a deposition tool, using a nitrous oxide plasma. The plasma treatment prepares the exposed SOG surface for an in situ deposition of a thick silicon nitride layer, by improving the adhesion of thick silicon nitride to the underlying SOG layer, and by decreasing the possibility of silicon nitride delamination, that can occur with counterparts, fabricated without the nitrous oxide plasma treatment of the SOG layer.
摘要翻译：已经开发了用于改善厚氮化硅层与玻璃上的底层旋涂（SOG）层的粘附性的方法。施加，烘烤和固化SOG层之后，使用一氧化二氮等离子体在沉积工具中进行SOG层的等离子体处理。等离子体处理通过改善厚氮化硅与下面的SOG层的粘附性以及通过降低可能与对应物发生的氮化硅分层的可能性来制备暴露的SOG表面，用于原位沉积厚的氮化硅层，在没有氧化亚氮等离子体处理SOG层的情况下制造。

10. 发明授权

US06287172B1 Method for improvement of tungsten chemical-mechanical polishing process 有权
标题翻译：钨化学机械抛光工艺的改进方法
公开(公告)号：US06287172B1
公开(公告)日：2001-09-11
申请号：US09465700
申请日：1999-12-17
申请人： Tong-Hua Kuan , Hui-Ling Wang , Ying-Lang Wang , Chin-Kun Lan
发明人： Tong-Hua Kuan , Hui-Ling Wang , Ying-Lang Wang , Chin-Kun Lan
IPC分类号： B24B100
CPC分类号： B24B37/345 , B24B37/0056 , B24B37/042 , B24D13/142
摘要： A multi-step chemical-mechanical polishing method for improving tungsten chemical-mechanical polishing (CMP) process is provided in the present invention. The method comprises following steps. First, a wafer is placed on a first pad of a CMP system, wherein a head fixes the wafer on the first pad. Then, the head is rotated and the wafer is polished on the first pad by using a tungsten slurry. Next, the wafer is transferred to place on a second pad of the CMP system, wherein the head fixes the wafer on the second pad. Following, the head is rotated and the wafer is polished on the second pad by using the tungsten slurry. Then, the wafer is cleaned on the second pad by using a de-ionic water. Next, the wafer is transferred to place on a third pad of the CMP system, wherein the head fixes the wafer on the third pad. Following, the wafer is cleaned on the third pad by using the de-ionic water. Last, the head is rotated and the wafer is polished on the third pad by using an oxide slurry, wherein a pH value of the tungsten slurry and a pH value of the oxide slurry are opposite.
摘要翻译：本发明提供了一种用于改善钨化学机械抛光（CMP）工艺的多步化学机械抛光方法。该方法包括以下步骤。首先，将晶片放置在CMP系统的第一焊盘上，其中头部将晶片固定在第一焊盘上。然后，头部旋转，并且通过使用钨浆料在第一焊盘上抛光晶片。接下来，将晶片转移到CMP系统的第二焊盘上，其中头部将晶片固定在第二焊盘上。接下来，头部旋转，并且通过使用钨浆料在第二垫上抛光晶片。然后，通过使用脱离子水在第二焊盘上清洁晶片。接下来，将晶片转移到CMP系统的第三焊盘上，其中头部将晶片固定在第三焊盘上。接下来，通过使用去离子水在第三垫上清洁晶片。最后，旋转头部，通过使用氧化物浆料在第三焊盘上抛光晶片，其中钨浆料的pH值和氧化物浆料的pH值相反。

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