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1. 发明申请

US20110241179A1 DIFFUSION REGION ROUTING FOR NARROW SCRIBE-LINE DEVICES 有权
标题翻译：用于NARROW SCRIBE-LINE设备的扩展区域路由
公开(公告)号：US20110241179A1
公开(公告)日：2011-10-06
申请号：US13164523
申请日：2011-06-20
申请人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
发明人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
IPC分类号： H01L23/544
CPC分类号： H01L23/585 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
摘要翻译：本公开提供了一种制造集成电路（IC）装置的方法。该方法包括在半导体衬底中形成第一IC特征和第二IC特征，第一和第二IC特征彼此间隔开并由划线区分开; 在所述半导体衬底中至少部分地在所述划线区域内形成掺杂的布线特征并且被配置为连接所述第一和第二IC特征; 在所述半导体衬底上形成多层互连（MLI）结构和层间电介质（ILD），其中所述MLI被配置为在所述划线区域内不存在; 并且在刻划区域内蚀刻ILD和半导体衬底以形成划线沟槽。

2. 发明授权

US07968431B2 Diffusion region routing for narrow scribe-line devices 有权
标题翻译：窄划线设备的扩散区域路由
公开(公告)号：US07968431B2
公开(公告)日：2011-06-28
申请号：US12173121
申请日：2008-07-15
申请人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
发明人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
IPC分类号： H01L23/544
CPC分类号： H01L23/585 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
摘要翻译：本公开提供了一种制造集成电路（IC）装置的方法。该方法包括在半导体衬底中形成第一IC特征和第二IC特征，第一和第二IC特征彼此间隔开并由划线区分开; 在所述半导体衬底中至少部分地在所述划线区域内形成掺杂的布线特征并且被配置为连接所述第一和第二IC特征; 在所述半导体衬底上形成多层互连（MLI）结构和层间电介质（ILD），其中所述MLI被配置为在所述划线区域内不存在; 并且在刻划区域内蚀刻ILD和半导体衬底以形成划线沟槽。

3. 发明授权

US08669641B2 Diffusion region routing for narrow scribe-line devices 有权
标题翻译：窄划线设备的扩散区域路由
公开(公告)号：US08669641B2
公开(公告)日：2014-03-11
申请号：US13164523
申请日：2011-06-20
申请人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
发明人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
IPC分类号： H01L21/78
CPC分类号： H01L23/585 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
摘要翻译：本公开提供了一种制造集成电路（IC）装置的方法。该方法包括在半导体衬底中形成第一IC特征和第二IC特征，第一和第二IC特征彼此间隔开并由划线区分开; 在所述半导体衬底中至少部分地在所述划线区域内形成掺杂的布线特征并且被配置为连接所述第一和第二IC特征; 在所述半导体衬底上形成多层互连（MLI）结构和层间电介质（ILD），其中所述MLI被配置为在所述划线区域内不存在; 并且在刻划区域内蚀刻ILD和半导体衬底以形成划线沟槽。

4. 发明申请

US20100013059A1 DIFFUSION REGION ROUTING FOR NARROW SCRIBE-LINE DEVICES 有权
标题翻译：用于NARROW SCRIBE-LINE设备的扩展区域路由
公开(公告)号：US20100013059A1
公开(公告)日：2010-01-21
申请号：US12173121
申请日：2008-07-15
申请人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
发明人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
IPC分类号： H01L21/302 , H01L23/544
CPC分类号： H01L23/585 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
摘要翻译：本公开提供了一种制造集成电路（IC）装置的方法。该方法包括在半导体衬底中形成第一IC特征和第二IC特征，第一和第二IC特征彼此间隔开并由划线区分开; 在所述半导体衬底中至少部分地在所述划线区域内形成掺杂的布线特征并且被配置为连接所述第一和第二IC特征; 在所述半导体衬底上形成多层互连（MLI）结构和层间电介质（ILD），其中所述MLI被配置为在所述划线区域内不存在; 并且在刻划区域内蚀刻ILD和半导体衬底以形成划线沟槽。

5. 发明申请

US20060113640A1 Method and apparatus for polymer dielectric surface recovery by ion implantation 有权
标题翻译：用离子注入聚合物电介质表面回收的方法和装置
公开(公告)号：US20060113640A1
公开(公告)日：2006-06-01
申请号：US10998423
申请日：2004-11-29
申请人： Hsiu-Mei Yu , Ken-Shen Chou , Shun-Liang Hsu
发明人： Hsiu-Mei Yu , Ken-Shen Chou , Shun-Liang Hsu
IPC分类号： H01L23/58
CPC分类号： H01L23/3114 , H01L24/11 , H01L24/12 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05647 , H01L2224/13099 , H01L2224/16 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/014 , H01L2924/12044 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/01028 , H01L2924/013
摘要： In one embodiment, the disclosure relates to a method and apparatus for surface recovery of a polymer insulation layer through implantation. The method includes providing a substrate having thereon a conductive pad and an insulation layer, optionally processing the conductive pad to remove oxide layer formed on the conductive pad and conducting ion implantation to recover dielectric properties of the insulation layer.
摘要翻译：在一个实施方案中，本公开涉及通过注入表面回收聚合物绝缘层的方法和装置。该方法包括提供其上具有导电焊盘和绝缘层的衬底，任选地处理导电焊盘以去除形成在导电焊盘上的氧化物层并导电离子注入以恢复绝缘层的介电性能。

6. 发明授权

US08624392B2 Electrical connection for chip scale packaging 有权
标题翻译：电子连接用于芯片级包装
公开(公告)号：US08624392B2
公开(公告)日：2014-01-07
申请号：US13152734
申请日：2011-06-03
申请人： Ming-Chih Yew , Fu-Jen Li , Po-Yao Lin , Chia-Jen Cheng , Hsiu-Mei Yu
发明人： Ming-Chih Yew , Fu-Jen Li , Po-Yao Lin , Chia-Jen Cheng , Hsiu-Mei Yu
IPC分类号： H01L23/485
CPC分类号： H01L24/13 , H01L21/76885 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/82 , H01L2224/02235 , H01L2224/02255 , H01L2224/0235 , H01L2224/02375 , H01L2224/0401 , H01L2224/05005 , H01L2224/05008 , H01L2224/05022 , H01L2224/05541 , H01L2224/05569 , H01L2224/05572 , H01L2224/10155 , H01L2224/13005 , H01L2224/13006 , H01L2224/13007 , H01L2224/13024 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2924/00014 , H01L2924/01029 , H01L2924/351 , H01L2924/35121 , H01L2924/207 , H01L2924/2076 , H01L2224/05552
摘要： A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.
摘要翻译：提供了一种用于提供后钝化和欠掺杂金属化的系统和方法。一个实施例包括大于上覆下凸点金属化的后钝化层。延伸超过下凸块金属化的后钝化层屏蔽下层不受材料的热膨胀系数的不匹配产生的应力。

7. 发明申请

US20080303154A1 Through-silicon via interconnection formed with a cap layer 审中-公开
标题翻译：通过与盖层形成的通孔的通硅
公开(公告)号：US20080303154A1
公开(公告)日：2008-12-11
申请号：US11811660
申请日：2007-06-11
申请人： Hon-Lin Huang , Boe Su , Li-Hsin Tseng , Chia-Jen Cheng , Hsiu-Mei Yu
发明人： Hon-Lin Huang , Boe Su , Li-Hsin Tseng , Chia-Jen Cheng , Hsiu-Mei Yu
IPC分类号： H01L23/528 , H01L21/4763
CPC分类号： H01L23/53238 , H01L21/6836 , H01L21/76898 , H01L24/05 , H01L2221/6834 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/04941 , H01L2924/14 , H01L2924/19041 , H01L2924/19043
摘要： An integrated circuit structure and methods for forming the same are provided. The method includes providing a substrate; forming a through-silicon via (TSV) opening extending into the substrate; forming an under-bump metallurgy (UBM) in the TSV opening, wherein the UBM extends out of the TSV opening; filling the TSV opening with a metallic material; forming a patterned cap layer on the metallic material; and etching a portion of the UBM outside the TSV opening, wherein the patterned cap layer is used as a mask.
摘要翻译：提供一种集成电路结构及其形成方法。该方法包括提供基板; 形成延伸到衬底中的穿硅通孔（TSV）开口; 在TSV开口中形成凸块下冶金（UBM），其中UBM延伸出TSV开口; 用金属材料填充TSV开口; 在所述金属材料上形成图案化的盖层; 并且将所述UBM的一部分蚀刻在所述TSV开口外部，其中所述图案化盖层用作掩模。

8. 发明授权

US07378724B2 Cavity structure for semiconductor structures 有权
标题翻译：半导体结构的腔结构
公开(公告)号：US07378724B2
公开(公告)日：2008-05-27
申请号：US11166454
申请日：2005-06-24
申请人： Hsiu-Mei Yu , Gil Huang , Chien-Tung Yu , Owen Chen
发明人： Hsiu-Mei Yu , Gil Huang , Chien-Tung Yu , Owen Chen
IPC分类号： H01L23/02
CPC分类号： H01L27/14618 , H01L27/14632 , H01L27/14687 , H01L2924/0002 , H01L2924/00
摘要： A method for providing a cavity structure on a semiconductor device is provided. The method of forming the cavity structure, which may be particularly useful in packaging an image sensor, includes forming a spacer layer over a substrate. The spacer layer may be formed from a photo-sensitive material which may be patterned using photolithography techniques to form cavity walls surrounding dies on the wafer. A packaging layer, such as a substantially transparent layer, may be placed directly upon the cavity walls prior to curing. In another embodiment, the cavity walls are cured, an adhesive is applied to a surface of the cavity walls, and the packaging layer placed upon the adhesive. Thereafter, the wafer may be diced and the individual dies may be packaged for use.
摘要翻译：提供了一种在半导体器件上提供空腔结构的方法。在封装图像传感器中特别有用的形成腔结构的方法包括在衬底上形成间隔层。间隔层可以由感光材料形成，光敏材料可以使用光刻技术进行图案化以在晶片上形成周围的模具的空腔壁。包装层，例如基本上透明的层，可以在固化之前直接放置在空腔壁上。在另一个实施例中，空腔壁被固化，将粘合剂施加到空腔壁的表面，并且将包装层放置在粘合剂上。此后，可以对晶片进行切割，并且可以将各个管芯封装使用。

9. 发明授权

US08048778B1 Methods of dicing a semiconductor structure 有权
标题翻译：切割半导体结构的方法
公开(公告)号：US08048778B1
公开(公告)日：2011-11-01
申请号：US12964964
申请日：2010-12-10
申请人： Chin-Yu Ku , Hsiu-Mei Yu , Chun-Ying Lin , Young-Chang Lien , Sheng-Hsiang Chiu , Ta-Jen Yu
发明人： Chin-Yu Ku , Hsiu-Mei Yu , Chun-Ying Lin , Young-Chang Lien , Sheng-Hsiang Chiu , Ta-Jen Yu
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , B23K26/0006 , B23K26/009 , B23K26/18 , B23K26/364 , B23K26/40 , B23K2103/172 , B23K2103/42 , B23K2103/50 , H01L23/585 , H01L24/11 , H01L24/13 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/11849 , H01L2224/131 , H01L2224/13147 , H01L2924/01019 , H01L2924/14 , H01L2924/014 , H01L2924/00014 , H01L2924/00 , H01L2924/013
摘要： An embodiment of the disclosure includes a method of dicing a semiconductor structure. A device layer on a semiconductor substrate is provided. The device layer has a first chip region and a second chip region. A scribe line region is between the first chip region and the second chip region. A protective layer is formed over the device layer thereby over the semiconductor substrate. The protective layer on the scribe line region is laser sawn to form a notch. The notch extends into the semiconductor substrate and the protective layer is formed to cover a portion of the notch. A mechanically sawing is performed through the portion of the protective layer and the substrate to separate the first chip region and the second chip region.
摘要翻译：本公开的实施例包括切割半导体结构的方法。提供半导体衬底上的器件层。器件层具有第一芯片区域和第二芯片区域。划线区域在第一芯片区域和第二芯片区域之间。在器件层上形成保护层，从而在半导体衬底上形成保护层。切割线区域上的保护层被激光锯切以形成切口。凹口延伸到半导体衬底中，形成保护层以覆盖凹口的一部分。通过保护层和衬底的部分进行机械锯切以分离第一芯片区域和第二芯片区域。

10. 发明授权

US07863742B2 Back end integrated WLCSP structure without aluminum pads 有权
标题翻译：后端集成WLCSP结构，无铝焊盘
公开(公告)号：US07863742B2
公开(公告)日：2011-01-04
申请号：US11933572
申请日：2007-11-01
申请人： Hsiu-Mei Yu , Tjandra Winata Karta , Daniel Yang , Shih-Ming Chen , Chia-Jen Cheng
发明人： Hsiu-Mei Yu , Tjandra Winata Karta , Daniel Yang , Shih-Ming Chen , Chia-Jen Cheng
IPC分类号： H01L23/488
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05008 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/11 , H01L2224/1147 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2224/45124 , H01L2924/00011 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/00 , H01L2224/48 , H01L2224/05552 , H01L2924/01004 , H01L2924/013 , H01L2924/01028 , H01L2924/0105
摘要： An integrated circuit structure includes a passivation layer; a via opening in the passivation layer; a copper-containing via in the via opening; a polymer layer over the passivation layer, wherein the polymer layer comprises an aperture, and wherein the copper-containing via is exposed through the aperture; a post-passivation interconnect (PPI) line over the polymer layer, wherein the PPI line extends into the aperture and physically contacts the copper-via opening; and an under-bump metallurgy (UBM) over and electrically connected to the PPI line.
摘要翻译：集成电路结构包括钝化层; 钝化层中的通孔; 通孔开口中的含铜通孔; 在所述钝化层上的聚合物层，其中所述聚合物层包括孔，并且其中所述含铜通孔通过所述孔露出; 在聚合物层上方的钝化后互连（PPI）线，其中PPI线延伸到孔中并物理接触铜通孔; 以及在PPI线上电连接的凸块下冶金（UBM）。

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