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1. 发明申请

US20180166380A1 VERTICAL SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180166380A1
公开(公告)日：2018-06-14
申请号：US15620870
申请日：2017-06-13
申请人： Jo-young Park , Chang-seok Kang , Chang-sup Lee , Se-mee Jang
发明人： Jo-young Park , Chang-seok Kang , Chang-sup Lee , Se-mee Jang
IPC分类号： H01L23/522 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L23/528 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76877 , H01L27/11548 , H01L27/11556 , H01L27/11575 , H01L27/11582
摘要： A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.

2. 发明申请

US20150060979A1 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US20150060979A1
公开(公告)日：2015-03-05
申请号：US14471619
申请日：2014-08-28
申请人： Gil-Sung Lee , Chang-Seok Kang , Ju-Hyung Kim
发明人： Gil-Sung Lee , Chang-Seok Kang , Ju-Hyung Kim
IPC分类号： H01L27/115 , H01L29/10 , H01L29/423
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/105 , H01L29/42356
摘要： A vertical memory device includes a channel and gate electrodes. The channel extends in a vertical direction with respect to a top surface of a substrate. The gate electrodes are disposed on an outer sidewall of the channel. The gate electrodes includes a ground selection line (GSL), a word line, a string selection line (SSL) and a first dummy word line sequentially stacked from the top surface of the substrate in the vertical direction to be spaced apart from each other. The channel includes an impurity region at a portion adjacent to the SSL.
摘要翻译：垂直存储器件包括沟道和栅电极。通道相对于基板的顶表面在垂直方向上延伸。栅电极设置在通道的外侧壁上。栅极电极包括从基板的上表面沿垂直方向依次堆叠的接地选择线（GSL），字线，串选择线（SSL）和第一虚拟字线，以彼此间隔开。该通道在与SSL相邻的部分包括杂质区域。

3. 发明授权

US08877591B2 Methods of manufacturing vertical structure nonvolatile memory devices 有权
标题翻译：制造垂直结构非易失性存储器件的方法
公开(公告)号：US08877591B2
公开(公告)日：2014-11-04
申请号：US14092191
申请日：2013-11-27
申请人： Byeong-in Choe , Sung-il Chang , Chang-seok Kang , Jin-soo Lim
发明人： Byeong-in Choe , Sung-il Chang , Chang-seok Kang , Jin-soo Lim
IPC分类号： H01L21/336 , H01L29/78 , G11C16/04 , H01L29/66 , H01L29/792 , H01L27/115 , H01L29/788
CPC分类号： H01L29/66666 , G11C16/0466 , G11C16/0483 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7827 , H01L29/7889 , H01L29/7926
摘要： A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends.
摘要翻译：垂直结构的非易失性存储器件可以包括在衬底上沿垂直方向延伸的沟道层。存储单元串包括沿着沟道层的垂直侧壁在垂直方向上设置在基板上的多个晶体管。多个晶体管中的至少一个晶体管包括在晶体管的栅极中的至少一个凹部，至少一个包括沟道层的突起延伸到该凹槽中。

4. 发明申请

US20130228849A1 NONVOLATILE MEMORY DEVICE AND FABRICATING METHOD THEREOF 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20130228849A1
公开(公告)日：2013-09-05
申请号：US13775833
申请日：2013-02-25
申请人： Ju-Hyung Kim , Chang-Seok Kang , Woon-Kyung Lee
发明人： Ju-Hyung Kim , Chang-Seok Kang , Woon-Kyung Lee
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L29/792 , H01L27/11582 , H01L29/4234 , H01L29/513 , H01L29/66833 , H01L29/7926
摘要： A nonvolatile memory device comprises a channel pattern, a first interlayer dielectric film and a second interlayer dielectric film spaced apart from each other and stacked over each other, a gate pattern disposed between the first interlayer dielectric film and the second interlayer dielectric film, a trap layer disposed between the gate pattern and the channel pattern and a charge spreading inhibition layer disposed between the channel pattern and the first interlayer dielectric film and between the channel pattern and the second interlayer dielectric film. The charge spreading inhibition layer may include charges inside or on its surface. The charge spreading inhibition layer includes at least one of a metal oxide film or a metal nitride film or a metal oxynitride film having a greater dielectric constant than a silicon oxide film.
摘要翻译：非易失性存储器件包括彼此间隔开并且彼此堆叠的沟道图案，第一层间电介质膜和第二层间电介质膜，布置在第一层间电介质膜和第二层间电介质膜之间的栅极图案，阱设置在栅极图案和沟道图案之间的层，以及设置在沟道图案和第一层间电介质膜之间以及沟道图案和第二层间电介质膜之间的电荷扩展抑制层。电荷扩散抑制层可以包括其表面内部或其表面上的电荷。电荷扩散抑制层包括金属氧化物膜或金属氮化物膜或具有比氧化硅膜更大的介电常数的金属氧氮化物膜中的至少一种。

5. 发明申请

US20120068245A1 NON-VOLATILE MEMORY DEVICES INCLUDING BLOCKING INSULATION PATTERNS WITH SUB-LAYERS HAVING DIFFERENT ENERGY BAND GAPS 有权
标题翻译：非易失性存储器件，包括具有不同能量带GAAS的子层的阻塞绝缘图案
公开(公告)号：US20120068245A1
公开(公告)日：2012-03-22
申请号：US13305930
申请日：2011-11-29
申请人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
发明人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11517 , H01L27/11529 , H01L27/11563 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/42348 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7883
摘要： A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底和半导体衬底上的隔离层，其中隔离层限定半导体衬底的有源区。可以在半导体衬底的有源区上设置隧道绝缘层，并且可以在隧道绝缘层上设置电荷存储图案。可以在电荷存储图案上提供界面层图案，并且可以在界面层图案上提供阻挡绝缘图案。此外，块绝缘图案可以包括高k介电材料，并且界面层图案和阻挡绝缘图案可以包括不同的材料。可以在阻挡绝缘层上设置控制栅电极，使得阻挡绝缘图案位于界面层图案和控制栅电极之间。还讨论了相关方法。

6. 发明申请

US20110198685A1 Non-Volatile Memory Devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US20110198685A1
公开(公告)日：2011-08-18
申请号：US13095408
申请日：2011-04-27
申请人： Hyun-Suk Kim , Sun-II Shim , Chang-Seok Kang , Won-Cheol Jeong , Jung-Dal Choi , Jae-Kwan Park , Seung-Hyun Lim , Sun-Jung Kim
发明人： Hyun-Suk Kim , Sun-II Shim , Chang-Seok Kang , Won-Cheol Jeong , Jung-Dal Choi , Jae-Kwan Park , Seung-Hyun Lim , Sun-Jung Kim
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L29/42324 , H01L29/4234 , H01L29/7881 , H01L29/792
摘要： Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.
摘要翻译：提供了非易失性存储器件，其包括在衬底上的控制栅电极; 在控制栅电极和衬底之间的电荷存储绝缘层; 在电荷存储绝缘层和衬底之间的隧道绝缘层; 电荷存储绝缘层和控制栅电极之间的阻挡绝缘层; 以及隧道绝缘层和阻挡绝缘层之间的材料层，材料层具有构成势阱底部的能级。

7. 发明授权

US07776687B2 Semiconductor device having a gate contact structure capable of reducing interfacial resistance and method of forming the same 有权
标题翻译：具有能够降低界面电阻的栅极接触结构的半导体器件及其形成方法
公开(公告)号：US07776687B2
公开(公告)日：2010-08-17
申请号：US11797401
申请日：2007-05-03
申请人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
发明人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/823462 , H01L21/823475 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.
摘要翻译：半导体器件具有栅极接触结构，包括半导体衬底，用作晶体管的栅电极的多晶硅层，中间导电层，具有暴露多晶硅层的开口的顶部金属层和直接接触的接触插塞使多晶硅层通过开口接触。

8. 发明授权

US07772639B2 Charge-trap nonvolatile memory devices 有权
标题翻译：充电陷阱非易失性存储器件
公开(公告)号：US07772639B2
公开(公告)日：2010-08-10
申请号：US11700315
申请日：2007-01-31
申请人： Chang-Seok Kang , Jung-Dal Choi , Ju-Hyung Kim , Jong-Sun Sel , Jae-Sung Sim , Sang-Hun Jeon
发明人： Chang-Seok Kang , Jung-Dal Choi , Ju-Hyung Kim , Jong-Sun Sel , Jae-Sung Sim , Sang-Hun Jeon
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L27/115
摘要： Nonvolatile memory devices including device isolation patterns on a semiconductor substrate are provided. The device isolation patterns define a cell active region and a peripheral active region of the semiconductor substrate. Cell gate electrodes are provided that cross over the cell active regions. Memory cell patterns are provided between the cell gate electrodes and the cell active regions and extend toward the device isolation patterns. A tunnel insulation film is provided between the memory cell pattern and the cell active region. Related methods of fabricating nonvolatile memory devices are also provided herein.
摘要翻译：提供包括半导体衬底上的器件隔离图案的非易失性存储器件。器件隔离图案限定半导体衬底的单元有源区和外围有源区。提供跨越电池有源区的电池栅电极。在单元栅极电极和单元有源区之间提供存储单元图案，并朝向器件隔离图案延伸。在存储单元图形和单元有源区之间设置隧道绝缘膜。本文还提供了制造非易失性存储器件的相关方法。

9. 发明授权

US07399672B2 Methods of forming nonvolatile memory devices 有权
标题翻译：形成非易失性存储器件的方法
公开(公告)号：US07399672B2
公开(公告)日：2008-07-15
申请号：US11375983
申请日：2006-03-15
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , B82Y10/00 , H01L21/823462 , H01L27/0629 , H01L27/11526 , H01L27/11546 , H01L27/11568
摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.
摘要翻译：形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。在电阻器区域中的器件隔离层上形成第一导电层。半导体衬底暴露在电池阵列区域中。在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分上形成电池绝缘层。在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

10. 发明申请

US20070257302A1 Semiconductor device having a gate contact structure capable of reducing interfacial resistance and method of forming the same 有权
标题翻译：具有能够降低界面电阻的栅极接触结构的半导体器件及其形成方法
公开(公告)号：US20070257302A1
公开(公告)日：2007-11-08
申请号：US11797401
申请日：2007-05-03
申请人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
发明人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/823462 , H01L21/823475 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.
摘要翻译：半导体器件具有栅极接触结构，包括半导体衬底，用作晶体管的栅电极的多晶硅层，中间导电层，具有暴露多晶硅层的开口的顶部金属层和直接接触的插塞使多晶硅层通过开口接触。

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