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1. 发明授权

US07131102B2 Full sized scattering bar alt-PSM technique for IC manufacturing in sub-resolution era 有权
公开(公告)号：US07131102B2
公开(公告)日：2006-10-31
申请号：US10782670
申请日：2004-02-19
申请人： Chang-Ming Dai , Chung-Hsing Chang , Jan-Wen You , Burn J. Lin
发明人： Chang-Ming Dai , Chung-Hsing Chang , Jan-Wen You , Burn J. Lin
IPC分类号： G06F17/50
CPC分类号： G03F1/32 , G03F1/30 , G03F1/70 , G03F7/2026
摘要： A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.

2. 发明授权

US06830702B2 Single trench alternating phase shift mask fabrication 失效
标题翻译：单沟槽交变相移掩模制造
公开(公告)号：US06830702B2
公开(公告)日：2004-12-14
申请号：US10165028
申请日：2002-06-07
申请人： San-De Tzu , Chang-Ming Dai , Chung-Hsing Chang , Chen-Hao Hsieh
发明人： San-De Tzu , Chang-Ming Dai , Chung-Hsing Chang , Chen-Hao Hsieh
IPC分类号： B44C122
CPC分类号： C03C17/3605 , C03C17/36 , C03C2218/33 , C23F4/00 , G03F1/30
摘要： The invention relates to fabricating a single-trench alternating phase shift mask (PSM). A chromium layer over a mask layer, which is itself over a quartz layer, of the PSM is patterned according to a semiconductor design. The mask layer and the quartz layer are dry etched through a photoresist layer that has been applied over the chromium layer and patterned according to an alternating PSM design. The dry etching initially forms single trenches of the PSM. The quartz layer is next wet etched through the mask layer to completely form the single trenches of the PSM, where the photoresist layer has first been removed. The mask layer is dry etched again, where the single trenches of the PSM are initially filled with filler material to protect the single trenches from the dry etching.
摘要翻译：本发明涉及制造单沟槽交替相移掩模（PSM）。根据半导体设计对PSM上的掩模层上的铬层本身在石英层上进行图案化。掩模层和石英层通过已经施加在铬层上并且根据交替的PSM设计被图案化的光致抗蚀剂层被干蚀刻。干蚀刻最初形成PSM的单个沟槽。接着通过掩模层湿法蚀刻石英层，以完全形成PSM的单个沟槽，其中光致抗蚀剂层首先被去除。再次对掩模层进行干蚀刻，其中PSM的单个沟槽最初用填充材料填充，以保护单个沟槽免受干蚀刻。

3. 发明授权

US6045954A Formation of silicon nitride film for a phase shift mask at 193 nm 失效
标题翻译：在193nm处形成用于相移掩模的氮化硅膜
公开(公告)号：US6045954A
公开(公告)日：2000-04-04
申请号：US97145
申请日：1998-06-12
申请人： Chang-Ming Dai , Lon A. Wang , H.L. Chen
发明人： Chang-Ming Dai , Lon A. Wang , H.L. Chen
IPC分类号： G03F1/00 , G03F1/32 , G03F9/00
CPC分类号： G03F1/32
摘要： A half tone phase shift mask material, suitable for use at 193 nm is disclosed. It comprises a layer of nitrogen rich silicon nitride that was formed by subjecting a mixture of a nitrogen bearing gas, such as nitrogen and/or ammonia, with a silicon bearing gas, such as silane, to a plasma discharge. Provided the ratio of the nitrogen bearing to the silicon bearing gases is about 10 to 1, films having the required optical properties at 193 nm are formed. These properties are a reflectance that is less than 15% and a transmittance that is between 4 and 15%. Related optical properties, namely an extinction coefficient of about 0.4 and a refractive index of about 2.5, are also closely approached. Additionally, the films are stable under prolonged UV exposure and exhibit good etch behavior.
摘要翻译：公开了适用于193nm的半色相相位掩模材料。它包括通过将诸如氮和/或氨的含氮气体的混合物与含硅气体如硅烷进行等离子体放电而形成的富氮氮化硅层。如果含氮气体与含硅气体的比率为约10比1，则形成在193nm具有所需光学性质的膜。这些性质是反射率小于15％，透射率在4和15％之间。相关的光学性质，即约0.4的消光系数和约2.5的折射率也是紧密接近的。另外，膜在长时间的UV曝光下是稳定的并且表现出良好的蚀刻行为。

4. 发明授权

US6040119A Elimination of proximity effect in photoresist 失效
标题翻译：消除光致抗蚀剂中的邻近效应
公开(公告)号：US6040119A
公开(公告)日：2000-03-21
申请号：US49213
申请日：1998-03-27
申请人： Tsai-Sheng Gau , Chang-Ming Dai
发明人： Tsai-Sheng Gau , Chang-Ming Dai
IPC分类号： G03F1/08 , G03F7/20 , G03F7/26 , G03F7/38 , H01L21/027
CPC分类号： G03F7/70425 , G03F7/2006 , G03F7/38
摘要： The proximity effect in photoresist patterns has been eliminated by carefully controlling the values of three independent variables that are involved in the photolithographic process. These are the temperature at which Post Exposure Bake is performed, the numerical aperture of the exposure system and the partial coherence parameter. Specifically, the Post Exposure Bake temperature should be 20-25.degree. C. lower than that recommended by the manufacturer, the numerical aperture should be around 0.5 and the partial coherence parameter around 0.8. If these guidelines are followed, no proximity effect is in evidence down to duty ratios less than 1 and distortion-free patterns are obtained without the need for an Optical Proximity Correction.
摘要翻译：通过仔细控制光刻工艺中涉及的三个独立变量的值，消除了光致抗蚀剂图案中的邻近效应。这些是进行曝光后烘烤的温度，曝光系统的数值孔径和部分相干参数。具体来说，曝光后烘烤温度应比制造商推荐的温度低20-25℃，数值孔径应在0.5左右，部分相干参数约为0.8。如果遵循这些指导原则，则无法将邻近效应降低到小于1的占空比，并且获得无失真模式，而无需光学邻近校正。

5. 发明授权

US5935762A Two-layered TSI process for dual damascene patterning 失效
标题翻译：双层镶嵌图案的双层TSI工艺
公开(公告)号：US5935762A
公开(公告)日：1999-08-10
申请号：US949358
申请日：1997-10-14
申请人： Chang-Ming Dai , Jammy Chin-Ming Huang
发明人： Chang-Ming Dai , Jammy Chin-Ming Huang
IPC分类号： G03F7/26 , H01L21/768
CPC分类号： H01L21/76811 , G03F7/265 , H01L21/76813
摘要： A new method is disclosed for forming dual damascene patterns using a silylation process. A substrate is provided with a tri-layer of insulation formed thereon. A first layer of silylation photoresist is formed on the substrate and is imaged with a hole pattern by exposure through a mask. Using a silylation process, which greatly improves the depth of focus by reducing reflections from the underlying substrate, the regions in the first photoresist adjacent to the hole pattern are affixed to form top surface imaging mask. The hole pattern is then etched in the first photoresist. A second layer of photoresist is formed, and is imaged with a line pattern aligned with the previous hole pattern by exposure through a mask. The line pattern in the second photoresist is etched. The hole pattern in the first photoresist is transferred into the top layer of composite insulation first and then into the middle etch-stop layer by successive etching. The line pattern in the second photoresist layer is transferred into the first photoresist layer through a subsequent resist dry etching process. Finally, the line pattern and the hole pattern are transferred simultaneously into the top and lower layers of the composite insulation layer, respectively, through a final dry oxide etching. Having thus formed the integral hole and line patterns into the insulation layer, metal is deposited into the dual damascene pattern. Any excess metal on the surface of the insulating layer is then removed by any number of ways including chemical-mechanical polishing, thereby planarizing the surface and readying it for the next semiconductor process.
摘要翻译：公开了一种使用甲硅烷基化方法形成双重镶嵌图案的新方法。衬底上形成有三层绝缘体。在衬底上形成第一层甲硅烷基化光致抗蚀剂，并通过掩模曝光以孔图案成像。使用甲硅烷基化方法，其通过减少来自下面的基底的反射而大大地改善了聚焦深度，邻近孔图案的第一光致抗蚀剂中的区域被固定以形成顶表面成像掩模。然后在第一光致抗蚀剂中蚀刻孔图案。形成第二层光致抗蚀剂，并通过通过掩模曝光以与先前孔图案对准的线图案成像。蚀刻第二光致抗蚀剂中的线图案。第一光致抗蚀剂中的孔图案首先转移到复合绝缘层的顶层中，然后通过连续蚀刻转移到中间蚀刻停止层。通过后续的抗蚀剂干法蚀刻工艺将第二光致抗蚀剂层中的线图案转移到第一光致抗蚀剂层中。最后，通过最终的干法氧化物蚀刻，将线图案和孔图案分别同时转印到复合绝缘层的顶层和下层。由此，将整体的孔和线图案形成为绝缘层，金属沉积到双镶嵌图案中。然后通过包括化学机械抛光在内的任何数量的方式去除绝缘层表面上的任何多余的金属，从而平坦化表面并准备下一个半导体工艺。

6. 发明授权

US07036108B2 Full sized scattering bar alt-PSM technique for IC manufacturing in sub-resolution era 有权
标题翻译：全尺寸散射棒alt-PSM技术用于分辨率时代的IC制造
公开(公告)号：US07036108B2
公开(公告)日：2006-04-25
申请号：US10781182
申请日：2004-02-18
申请人： Chang-Ming Dai , Chung-Hsing Chang , Jan-Wen You , Burn J. Lin
发明人： Chang-Ming Dai , Chung-Hsing Chang , Jan-Wen You , Burn J. Lin
IPC分类号： G06F17/50
CPC分类号： G03F1/32 , G03F1/30 , G03F1/70 , G03F7/2026
摘要： A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.
摘要翻译：描述了在制造集成电路期间同时缩小栅极长度和多晶硅互连的工艺。正色调光致抗蚀剂涂覆在基板上，并且首先用具有全尺寸散射条的交替相移掩模曝光，这使得栅极尺寸能够被印刷为曝光波长尺寸的1/4至1/2。然后使用具有镀铬阻挡区域的三次衰减相移掩模将衬底曝光，以保护收缩的栅极和具有散射棒的衰减区域以收缩互连线。散射棒不会印在光刻胶图案中。该方法比常规光刻方法提供更高的DOF，更低的OPE和更低的对透镜像差的灵敏度。提供了数据处理流程，其导致针对两个掩模中的每一个的修改的GDS布局。还包括用于生成相移布局数据的系统。

7. 发明授权

US5882996A Method of self-aligned dual damascene patterning using developer soluble arc interstitial layer 失效
标题翻译：使用显影剂可溶性电弧间隙层的自对准双镶嵌图案的方法
公开(公告)号：US5882996A
公开(公告)日：1999-03-16
申请号：US949354
申请日：1997-10-14
申请人： Chang-Ming Dai
发明人： Chang-Ming Dai
IPC分类号： H01L21/311 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76811 , H01L21/31144 , H01L21/76813
摘要： A method is disclosed for patterning dual damascene interconnections in semiconductor chips through the use of a developer soluble ARC interstitial layer. This is accomplished by providing a silicon substrate having a composite layer of insulation deposited thereon whereby said composite layer comprises a first layer of dielectric separated from a second layer of dielectric by an intervening intermediate layer of silicon nitride. Then, two layers of photoresist are deposited with an intervening interstitial layer of water soluble anti-reflective coating (ARC). The ARC, having a relatively high refractive index, serves as a barrier to light so that the top layer of photoresist is first line patterned without affecting the second layer. The second layer of photoresist is next hole patterned. The hole pattern is transferred into the top dielectric layer and the intervening silicon nitride layer by etching. The line pattern in the first photoresist layer is etched into the top dielectric layer at the same time the hole pattern is transferred from the top dielectric layer into the bottom dielectric layer by the same etching process. The photoresist layers are then removed and the dual damascene structure thusly formed is filled with metal forming the metal line and hole interconnection on the semiconductor substrate.
摘要翻译：公开了通过使用显影剂可溶性ARC间隙层来在半导体芯片中图案化双镶嵌互连的方法。这通过提供具有沉积在其上的绝缘复合层的硅衬底来实现，其中所述复合层包括通过中间氮化硅中间层从第二电介质层分离的第一介电层。然后，用水溶性抗反射涂层（ARC）的中间间隙层沉积两层光致抗蚀剂。具有相对较高折射率的ARC用作光的屏障，使得光致抗蚀剂的顶层是第一线图案化而不影响第二层。第二层光致抗蚀剂是下一孔图案。孔图案通过蚀刻转移到顶部介电层和中间氮化硅层中。通过相同的蚀刻工艺，将第一光致抗蚀剂层中的线图案蚀刻到顶部电介质层中，同时孔图案从顶部电介质层转移到底部电介质层。然后去除光致抗蚀剂层，并且由此形成的双镶嵌结构填充有形成半导体衬底上的金属线和空穴互连的金属。

8. 发明授权

US5691215A Method for fabricating a sub-half micron MOSFET device with insulator filled shallow trenches planarized via use of negative photoresist and de-focus exposure 失效
标题翻译：用于制造具有绝缘体填充的浅沟槽的半微米MOSFET器件的方法，其通过使用负光致抗蚀剂和脱焦曝光而平坦化
公开(公告)号：US5691215A
公开(公告)日：1997-11-25
申请号：US703084
申请日：1996-08-26
申请人： Chang-Ming Dai , Hong-Chang Dai , Shih-Chang Tai
发明人： Chang-Ming Dai , Hong-Chang Dai , Shih-Chang Tai
IPC分类号： H01L21/3105 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/31055
摘要： A process for globally planarizing the insulator used to fill narrow and wide shallow trenches, used in a MOSFET device, structure, has been developed. The process features smoothing the topography that exists after the insulator filling of narrow and shallow trenches, by creating photoresist plugs, only in the depressed topography regions. This is accomplished using a negative photoresist layer, a de-focus exposure, and the identical mask used to create the shallow trench pattern in a positive photoresist layer. A RIE procedure, with a 1:1 etch selectivity, is used to complete the planarization process.
摘要翻译：已经开发了用于全局平坦化用于填充用于MOSFET器件结构的窄且宽的浅沟槽的绝缘体的工艺。该过程的特征是通过仅在凹陷的地形区域中产生光致抗蚀剂插塞来平滑在狭窄和浅沟槽的绝缘体填充之后存在的形貌。这是使用负光致抗蚀剂层，去焦曝光和用于在正性光致抗蚀剂层中产生浅沟槽图案的相同掩模来实现的。使用具有1：1蚀刻选择性的RIE程序来完成平坦化过程。

9. 发明授权

US06711732B1 Full sized scattering bar alt-PSM technique for IC manufacturing in sub-resolution era 失效
公开(公告)号：US06711732B1
公开(公告)日：2004-03-23
申请号：US10205790
申请日：2002-07-26
申请人： Chang-Ming Dai , Chung-Hsing Chang , Jan-Wen You , Burn J. Lin
发明人： Chang-Ming Dai , Chung-Hsing Chang , Jan-Wen You , Burn J. Lin
IPC分类号： G06F1750
CPC分类号： G03F1/32 , G03F1/30 , G03F1/70 , G03F7/2026
摘要： A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.

10. 发明授权

US06291118B1 Elimination of proximity effect in photoresist 有权
标题翻译：消除光致抗蚀剂中的邻近效应
公开(公告)号：US06291118B1
公开(公告)日：2001-09-18
申请号：US09480266
申请日：2000-01-11
申请人： Tsai-Sheng Gau , Chang-Ming Dai
发明人： Tsai-Sheng Gau , Chang-Ming Dai
IPC分类号： G03F900
CPC分类号： G03F7/70425 , G03F7/2006 , G03F7/38
摘要： The proximity effect in photoresist patterns has been eliminated by carefully controlling the values of three independent variables that are involved in the photolithographic process. These are the temperature at which Post Exposure Bake is performed, the numerical aperture of the exposure system and the partial coherence parameter. Specifically, the Post Exposure Bake temperature should be 20-25° C. lower than that recommended by the manufacturer, the numerical aperture should be around 0.5 and the partial coherence parameter around 0.8. If these guidelines are followed, no proximity effect is in evidence down to duty ratios less than 1 and distortion-free patterns are obtained without the need for an Optical Proximity Correction.
摘要翻译：通过仔细控制光刻工艺中涉及的三个独立变量的值，消除了光致抗蚀剂图案中的邻近效应。这些是进行曝光后烘烤的温度，曝光系统的数值孔径和部分相干参数。具体来说，曝光后烘烤温度应比制造商建议的温度低20-25℃，数值孔径应在0.5左右，部分相干参数在0.8左右。如果遵循这些指导原则，则无法将邻近效应降低到小于1的占空比，并且获得无失真模式，而无需光学邻近校正。

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