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1. 发明授权

US07131102B2 Full sized scattering bar alt-PSM technique for IC manufacturing in sub-resolution era 有权
公开(公告)号：US07131102B2
公开(公告)日：2006-10-31
申请号：US10782670
申请日：2004-02-19
申请人： Chang-Ming Dai , Chung-Hsing Chang , Jan-Wen You , Burn J. Lin
发明人： Chang-Ming Dai , Chung-Hsing Chang , Jan-Wen You , Burn J. Lin
IPC分类号： G06F17/50
CPC分类号： G03F1/32 , G03F1/30 , G03F1/70 , G03F7/2026
摘要： A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.

2. 发明申请

US20050086629A1 Method of defining forbidden pitches for a lithography exposure tool 失效
公开(公告)号：US20050086629A1
公开(公告)日：2005-04-21
申请号：US10688500
申请日：2003-10-17
申请人： Jaw-Jung Shin , Chun-Kuang Chen , Tsai-Sheng Gau , Burn-Jeng Lin , Li-Chun Tien , Mi-Chang Chang , Yu-Jun Chou , Jan-Wen You , King-Chang Shu , Li-Jui Chen
发明人： Jaw-Jung Shin , Chun-Kuang Chen , Tsai-Sheng Gau , Burn-Jeng Lin , Li-Chun Tien , Mi-Chang Chang , Yu-Jun Chou , Jan-Wen You , King-Chang Shu , Li-Jui Chen
IPC分类号： G03F1/14 , G03F7/20 , G06F17/50
CPC分类号： G03F7/70641 , G03F1/44 , G03F7/70425 , G03F7/70433 , G03F7/705
摘要： A method of identifying and defining forbidden pitches or forbidden pitch ranges for a lithographic exposure tool under a given set of exposure conditions is provided. In the method, a computer simulation is performed, and its results are compared to frequently used pitches to see if such frequently used pitches may yield depth-of-focus (DOF) values greater than the focus budget for the exposure tool. If so, a verification test is performed by using a test mask and actually exposing a surface with the same pattern pitches simulated. From this, actual DOF values are obtained and compared to the focus budget of the exposure tool. Any pitches having a DOF value greater than the focus budget are designated as forbidden pitches. This forbidden pitch information may be integrated into a design rule to restrict the use of such forbidden pitches under the given exposure conditions where they are likely to arise.

3. 发明授权

US07175941B2 Phase shift assignments for alternate PSM 有权
标题翻译：替代PSM的相移分配
公开(公告)号：US07175941B2
公开(公告)日：2007-02-13
申请号：US10657503
申请日：2003-09-08
申请人： Jaw-Jung Shin , Jan-Wen You
发明人： Jaw-Jung Shin , Jan-Wen You
IPC分类号： G03F1/00 , G06F17/50
CPC分类号： G03F1/30 , G03F1/36
摘要： Prior art methods for forming alt. PSMs require a relatively large number of phase assignments to avoid phase conflicts in complex arrays. This has been improved by adding dummy elements at the ends of all rows and columns of the array that is to be imaged, while initially leaving all corners open. Phases are then assigned in checker board fashion to all elements. Additional dummy elements are then placed in the open corners and assigned the same phase as their immediate neighbors. The first exposure of the photoresist is made with both the original elements and the additional dummy elements. Then additional resist is coated and exposed and the original elements are open after development. If the added elements are made somewhat smaller than the original elements, only a single exposure is used.
摘要翻译：用于形成alt的现有技术方法。 PSM需要相对大量的相位分配以避免复杂阵列中的相位冲突。通过在要成像的数组的所有行和列的末尾添加虚拟元素，同时最初将所有角都打开，从而改善了这一点。然后将相位以棋盘方式分配给所有元素。然后将额外的虚拟元素放置在开放的角落并与其直接邻居分配相同的相位。光致抗蚀剂的第一曝光由原始元件和附加的虚拟元件两者制成。然后，另外的抗蚀剂被涂覆和暴露，并且原始元素在显影后是开放的。如果添加的元素略小于原始元素，则仅使用单次曝光。

4. 发明授权

US07013453B2 Full sized scattering bar alt-PSM technique for IC manufacturing in sub-resolution ERA 失效
标题翻译：全尺寸散射棒alt-PSM技术用于分辨率ERA中的IC制造
公开(公告)号：US07013453B2
公开(公告)日：2006-03-14
申请号：US10781176
申请日：2004-02-18
申请人： Chang-Ming Dai , Chung-Hsing Chang , Jan-Wen You , Burn J. Lin
发明人： Chang-Ming Dai , Chung-Hsing Chang , Jan-Wen You , Burn J. Lin
IPC分类号： G06F17/50
CPC分类号： G03F1/32 , G03F1/30 , G03F1/70 , G03F7/2026
摘要： A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.
摘要翻译：描述了在制造集成电路期间同时缩小栅极长度和多晶硅互连的工艺。正色调光致抗蚀剂涂覆在基板上，并且首先用具有全尺寸散射条的交替相移掩模曝光，这使得栅极尺寸能够被印刷为曝光波长尺寸的1/4至1/2。然后使用具有镀铬阻挡区域的三次衰减相移掩模将衬底曝光，以保护收缩的栅极和具有散射棒的衰减区域以收缩互连线。散射棒不会印在光刻胶图案中。该方法比常规光刻方法提供更高的DOF，更低的OPE和更低的对透镜像差的灵敏度。提供了数据处理流程，其导致针对两个掩模中的每一个的修改的GDS布局。还包括用于生成相移布局数据的系统。

5. 发明申请

US20070203680A1 Method and System for Identifying Lens Aberration Sensitive Patterns in an Integrated Circuit Chip 失效
标题翻译：用于识别集成电路芯片中的透镜畸变敏感图案的方法和系统
公开(公告)号：US20070203680A1
公开(公告)日：2007-08-30
申请号：US11421618
申请日：2006-06-01
申请人： Jaw-Jung Shin , King-Chang Shu , Jan-Wen You , Tsai-Sheng Gau
发明人： Jaw-Jung Shin , King-Chang Shu , Jan-Wen You , Tsai-Sheng Gau
IPC分类号： G06G7/48
CPC分类号： G03F7/70433 , G03F7/705 , G03F7/706
摘要： Disclosed is a method and a system for identifying lens aberration sensitive patterns in an integrated circuit chip. A first simulation of a layout is performed to simulate a contour without lens aberration. A second simulation is performed of the layout to simulate a contour with lens aberration. A difference of critical dimension is determined between the contours with and without lens aberration, and at least one lens aberration sensitive pattern is selected from a plurality of layouts based on the difference in critical dimension.
摘要翻译：公开了用于识别集成电路芯片中的透镜像差敏感图案的方法和系统。执行布局的第一模拟以模拟没有透镜像差的轮廓。执行布局以模拟具有透镜像差的轮廓的第二模拟。在具有和不具有透镜像差的轮廓之间确定临界尺寸的差异，并且基于临界尺寸的差异从多个布局中选择至少一个透镜像差敏感图案。

6. 发明授权

US07234128B2 Method for improving the critical dimension uniformity of patterned features on wafers 有权
标题翻译：改善晶片上图形特征的临界尺寸均匀性的方法
公开(公告)号：US07234128B2
公开(公告)日：2007-06-19
申请号：US10678788
申请日：2003-10-03
申请人： Tsai-Sheng Gau , Jaw-Jung Shin , Jan-Wen You , Burn-Jeng Lin
发明人： Tsai-Sheng Gau , Jaw-Jung Shin , Jan-Wen You , Burn-Jeng Lin
IPC分类号： G06F17/50 , G06F19/00 , G06K9/00
CPC分类号： G03F7/70616 , G03F7/70441 , G06T7/0004 , G06T2207/30148
摘要： A method for improving the critical dimension uniformity of a patterned feature on a wafer in semiconductor and mask fabrication is provided. In one embodiment, an evaluation means for evaluating the critical dimension distribution of a plurality of circuit layouts formed on the wafer, the plurality of circuit layouts defined by a mask is provided. A logic operation is performed on the plurality of circuit layouts to extract the patterned feature. The patterned feature is compared with design rules and if there is a deviation or difference between the patterned feature and the design rules, this difference is compensated for by adjusting photolithography adjustable parameters, such as, for example, mask-making.
摘要翻译：提供了一种用于改善半导体和掩模制造中的晶片上的图案化特征的临界尺寸均匀性的方法。在一个实施例中，提供了一种用于评估形成在晶片上的多个电路布局的临界尺寸分布的评估装置，提供了由掩模限定的多个电路布局。对多个电路布局执行逻辑操作以提取图案化特征。将图案特征与设计规则进行比较，并且如果图案特征和设计规则之间存在偏差或差异，则通过调整光刻可调参数（例如掩模制作）来补偿该差异。

7. 发明申请

US20070087291A1 Lithography process to reduce interference 审中-公开
标题翻译：光刻过程减少干扰
公开(公告)号：US20070087291A1
公开(公告)日：2007-04-19
申请号：US11252499
申请日：2005-10-18
申请人： Tsai-Sheng Gau , Jaw-Jung Shin , Chun-Kuang Chen , Jan-Wen You , Burn-Jeng Lin
发明人： Tsai-Sheng Gau , Jaw-Jung Shin , Chun-Kuang Chen , Jan-Wen You , Burn-Jeng Lin
IPC分类号： G03F7/20
CPC分类号： G03F7/70466 , G03F1/70 , G03F7/203 , G03F7/70425
摘要： A method and associated masks for carrying out a lithographic imaging process to reduce or avoid a strong interference effect in off-axis illumination, the method including providing a resist layer on a substrate; illuminating a first group of line patterns through a first mask on the resist layer; illuminating a second group of line patterns through a second mask on the resist layer, the second group of line patterns oriented nonparallel with respect to the first group of line patterns; and, developing the illuminated resist layer.
摘要翻译：一种用于进行光刻成像处理以减少或避免在离轴照明中的强干涉效应的方法和相关掩模，所述方法包括在基板上提供抗蚀剂层; 通过抗蚀剂层上的第一掩模照射第一组线图案; 通过抗蚀剂层上的第二掩模照射第二组线图案，第二组线条图案相对于第一组线图案取向不平行; 并且显影照射的抗蚀剂层。

8. 发明授权

US06973636B2 Method of defining forbidden pitches for a lithography exposure tool 失效
标题翻译：定义光刻曝光工具的禁止间距的方法
公开(公告)号：US06973636B2
公开(公告)日：2005-12-06
申请号：US10688500
申请日：2003-10-17
申请人： Jaw-Jung Shin , Chun-Kuang Chen , Tsai-Sheng Gau , Burn-Jeng Lin , Li-Chun Tien , Mi-Chang Chang , Yu-Jun Chou , Jan-Wen You , King-Chang Shu , Li-Jui Chen
发明人： Jaw-Jung Shin , Chun-Kuang Chen , Tsai-Sheng Gau , Burn-Jeng Lin , Li-Chun Tien , Mi-Chang Chang , Yu-Jun Chou , Jan-Wen You , King-Chang Shu , Li-Jui Chen
IPC分类号： G03F1/14 , G03F7/20 , G06F17/50
CPC分类号： G03F7/70641 , G03F1/44 , G03F7/70425 , G03F7/70433 , G03F7/705
摘要： A method of identifying and defining forbidden pitches or forbidden pitch ranges for a lithographic exposure tool under a given set of exposure conditions is provided. In the method, a computer simulation is performed, and its results are compared to frequently used pitches to see if such frequently used pitches may yield depth-of-focus (DOF) values greater than the focus budget for the exposure tool. If so, a verification test is performed by using a test mask and actually exposing a surface with the same pattern pitches simulated. From this, actual DOF values are obtained and compared to the focus budget of the exposure tool. Any pitches having a DOF value greater than the focus budget are designated as forbidden pitches. This forbidden pitch information may be integrated into a design rule to restrict the use of such forbidden pitches under the given exposure conditions where they are likely to arise.
摘要翻译：提供了一种在给定的曝光条件下识别和限定光刻曝光工具的禁止间距或禁止间距范围的方法。在该方法中，执行计算机模拟，并将其结果与经常使用的间距进行比较，以查看这种经常使用的间距是否可以产生比曝光工具的焦点预算大的焦点深度（DOF）值。如果是这样，则通过使用测试掩模执行验证测试，并且实际上暴露出模拟相同模式间距的表面。从此，获得实际的DOF值，并与曝光工具的焦点预算进行比较。 DOF值大于焦点预算的任何间距都被指定为禁止间距。该禁止音调信息可以被集成到设计规则中，以限制在可能出现的给定曝光条件下使用这种禁止间距。

9. 发明申请

US20050076323A1 Method for improving the critical dimension uniformity of patterned features on wafers 有权
标题翻译：改善晶片上图形特征的临界尺寸均匀性的方法
公开(公告)号：US20050076323A1
公开(公告)日：2005-04-07
申请号：US10678788
申请日：2003-10-03
申请人： Tsai-Sheng Gau , Jaw-Jung Shin , Jan-Wen You , Burn-Jeng Lin
发明人： Tsai-Sheng Gau , Jaw-Jung Shin , Jan-Wen You , Burn-Jeng Lin
IPC分类号： G03F7/20 , G06T7/00 , G06F17/50 , G06K9/00
CPC分类号： G03F7/70616 , G03F7/70441 , G06T7/0004 , G06T2207/30148
摘要： A method for improving the critical dimension uniformity of a patterned feature on a wafer in semiconductor and mask fabrication is provided. In one embodiment, an evaluation means for evaluating the critical dimension distribution of a plurality of circuit layouts formed on the wafer, the plurality of circuit layouts defined by a mask is provided. A logic operation is performed on the plurality of circuit layouts to extract the patterned feature. The patterned feature is compared with design rules and if there is a deviation or difference between the patterned feature and the design rules, this difference is compensated for by adjusting photolithography adjustable parameters, such as, for example, mask-making.
摘要翻译：提供了一种用于改善半导体和掩模制造中的晶片上的图案化特征的临界尺寸均匀性的方法。在一个实施例中，提供了一种用于评估形成在晶片上的多个电路布局的临界尺寸分布的评估装置，提供了由掩模限定的多个电路布局。对多个电路布局执行逻辑操作以提取图案化特征。将图案特征与设计规则进行比较，并且如果图案特征和设计规则之间存在偏差或差异，则通过调整光刻可调参数（例如掩模制作）来补偿该差异。

10. 发明授权

US06711732B1 Full sized scattering bar alt-PSM technique for IC manufacturing in sub-resolution era 失效
公开(公告)号：US06711732B1
公开(公告)日：2004-03-23
申请号：US10205790
申请日：2002-07-26
申请人： Chang-Ming Dai , Chung-Hsing Chang , Jan-Wen You , Burn J. Lin
发明人： Chang-Ming Dai , Chung-Hsing Chang , Jan-Wen You , Burn J. Lin
IPC分类号： G06F1750
CPC分类号： G03F1/32 , G03F1/30 , G03F1/70 , G03F7/2026
摘要： A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is ¼ to ½ the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.

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