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1. 发明授权

US08911551B2 Electroless plating apparatus and method 有权
标题翻译：化学镀设备及方法
公开(公告)号：US08911551B2
公开(公告)日：2014-12-16
申请号：US13196179
申请日：2011-08-02
申请人： Jason Chen , Nakano Liu , Winson Shao , Wen Chu , Chang-Hwang Hua
发明人： Jason Chen , Nakano Liu , Winson Shao , Wen Chu , Chang-Hwang Hua
IPC分类号： B05C11/00 , C23C18/16 , H01L21/768 , H01L21/288
CPC分类号： H01L21/288 , C23C18/1619 , C23C18/1666 , C23C18/1669 , H01L21/76843
摘要： An electroless plating apparatus and method designed specifically for plating at least one semiconductor wafer are disclosed. The apparatus comprises a container, a wafer holder, an electrolyte supplying unit, and an ultrasonic-vibration unit. The container is provided with at least an inlet and used for containing electrolyte. The wafer holder is provided within the container. The electrolyte supplying unit is used to supply the electrolyte into the container via the inlet. The ultrasonic-vibration unit consisting of at least one frequency ultrasonic transducer is disposed in the container for producing a uniform flow of electrolyte in the container. Thereby, the wafers can be uniformly plated, especially for wafers with fine via-holes or trench structures.
摘要翻译：公开了专门用于电镀至少一个半导体晶片的化学镀设备和方法。该装置包括容器，晶片保持器，电解质供给单元和超声波振动单元。容器设有至少一个入口并用于容纳电解质。晶片保持器设置在容器内。电解质供给单元用于经由入口将电解质供给到容器中。由至少一个频率超声波换能器组成的超声波振动单元设置在容器中，用于在容器中产生均匀的电解液流。因此，可以均匀地镀覆晶片，特别是对于具有精细通孔或沟槽结构的晶片。

2. 发明申请

US20110201192A1 METHOD OF PROCESSING BACKSIDE COPPER LAYER FOR SEMICONDUCTOR CHIPS 有权
标题翻译：用于半导体晶片的后端铜层的处理方法
公开(公告)号：US20110201192A1
公开(公告)日：2011-08-18
申请号：US12757458
申请日：2010-04-09
申请人： Chang-Hwang HUA , Wen Chu
发明人： Chang-Hwang HUA , Wen Chu
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L21/76849 , H01L21/76873 , H01L21/78 , H01L23/481 , H01L29/0657 , H01L29/41708 , H01L29/41725 , H01L2924/0002 , H01L2924/00
摘要： A method of processing copper backside metal layer for semiconductor chips is disclosed. The backside of a semiconductor wafer, with electronic devices already fabricated on the front side, is first coated with a thin metal seed layer by either electroless plating or sputtering. Then, the copper backside metal layer is coated on the metal seed layer. The metal seed layer not only increases the adhesion between the front side metal layer and the copper backside metal layer through backside via holes, but also prevents metal peeling from semiconductor's substrate after subsequent fabrication processes, which is helpful for increasing the reliability of device performances. Suitable materials for the metal seed layer includes Pd, Au, Ni, Ag, Co, Cr, Pt, or their alloys, such as NiP, NiB, AuSn, Pt—Rh and the likes. The use of Pd as seed layer is particularly useful for the copper backside metal layer, because the Pd layer also acts as a diffusion barrier to prevent Cu atoms entering the semiconductor wafer.
摘要翻译：公开了一种用于半导体芯片的铜背面金属层的处理方法。已经制造在前侧的电子器件的半导体晶片的背面首先通过化学镀或溅射涂覆有薄金属种子层。然后，将铜背面金属层涂覆在金属籽晶层上。金属种子层不仅通过背面通孔增加了前侧金属层和铜背面金属层之间的粘附性，而且还防止了后续制造工艺中的半导体基板的金属剥离，这有助于提高器件性能的可靠性。用于金属种子层的合适材料包括Pd，Au，Ni，Ag，Co，Cr，Pt或它们的合金，例如NiP，NiB，AuSn，Pt-Rh等。使用Pd作为种子层对于铜背面金属层特别有用，因为Pd层还用作扩散阻挡层以防止Cu原子进入半导体晶片。

3. 发明授权

US4978639A Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips 失效
标题翻译：在半导体芯片上同时形成通孔和环绕电镀的方法
公开(公告)号：US4978639A
公开(公告)日：1990-12-18
申请号：US295300
申请日：1989-01-10
申请人： Chang-Hwang Hua , Simon S. Chan , Ding-Yuan S. Day , Adrian C. Lee
发明人： Chang-Hwang Hua , Simon S. Chan , Ding-Yuan S. Day , Adrian C. Lee
IPC分类号： H01L21/288 , H01L21/768
CPC分类号： H01L21/78 , H01L21/288 , H01L21/76898 , Y10S148/028 , Y10S148/135 , Y10S438/977
摘要： Metallized via-holes and a wraparound metal plating are simultaneously formed on semiconductor chips by patterning a photoresist mask on the front surface of the wafer to open windows over metal pads as well as the grid areas where wraparound plating is desired; etching off the exposed metal if necessary and forming via-holes and grooves in the wafer by reactive ion etching to a depth which is less than the total thickness of the wafer; depositing a thin conductive film along the walls of the grooves and via-holes by electroless methods; plating the walls of the grooves and the via-holes with conductive metal by electrolytic methods; removing the back surface of the wafer ("backlapping") along with the floors of both the grooves and the via-holes, to expose the metal on the wall of the via-holes and separate the individual chips; and, depositing conductive metal on the back surface of the individual chips to complete the grounding path.
摘要翻译：在半导体芯片上同时形成金属化的通孔和环绕的金属电镀，方法是在晶片的前表面上形成光致抗蚀剂掩模以在金属焊盘上打开窗口以及需要环绕电镀的栅格区域; 如果需要则蚀刻暴露的金属，并通过反应离子蚀刻在晶片中形成通孔和沟槽，其深度小于晶片的总厚度; 通过化学镀方法沿沟槽和通孔的壁沉积薄导电膜; 通过电解方法用导电金属电镀槽和通孔; 与两个槽和通孔的地板一起去除晶片的背面（“后退”），以露出通孔壁上的金属并分离各个芯片; 并且在各个芯片的背面上沉积导电金属，以完成接地路径。

4. 发明授权

US08497206B2 Method of processing backside copper layer for semiconductor chips 有权
标题翻译：处理半导体芯片背面铜层的方法
公开(公告)号：US08497206B2
公开(公告)日：2013-07-30
申请号：US12757458
申请日：2010-04-09
申请人： Chang-Hwang Hua , Wen Chu
发明人： Chang-Hwang Hua , Wen Chu
IPC分类号： H01L21/441 , H01L29/41
CPC分类号： H01L21/76898 , H01L21/76849 , H01L21/76873 , H01L21/78 , H01L23/481 , H01L29/0657 , H01L29/41708 , H01L29/41725 , H01L2924/0002 , H01L2924/00
摘要： A method of processing copper backside metal layer for semiconductor chips is disclosed. The backside of a semiconductor wafer, with electronic devices already fabricated on the front side, is first coated with a thin metal seed layer by either electroless plating or sputtering. Then, the copper backside metal layer is coated on the metal seed layer. The metal seed layer not only increases the adhesion between the front side metal layer and the copper backside metal layer through backside via holes, but also prevents metal peeling from semiconductor's substrate after subsequent fabrication processes, which is helpful for increasing the reliability of device performances. Suitable materials for the metal seed layer includes Pd, Au, Ni, Ag, Co, Cr, Pt, or their alloys, such as NiP, NiB, AuSn, Pt—Rh and the likes. The use of Pd as seed layer is particularly useful for the copper backside metal layer, because the Pd layer also acts as a diffusion barrier to prevent Cu atoms entering the semiconductor wafer.
摘要翻译：公开了一种用于半导体芯片的铜背面金属层的处理方法。已经制造在前侧的电子器件的半导体晶片的背面首先通过化学镀或溅射涂覆有薄金属种子层。然后，将铜背面金属层涂覆在金属籽晶层上。金属种子层不仅通过背面通孔增加了前侧金属层和铜背面金属层之间的粘附性，而且还防止了后续制造工艺中的半导体基板的金属剥离，这有助于提高器件性能的可靠性。用于金属种子层的合适材料包括Pd，Au，Ni，Ag，Co，Cr，Pt或它们的合金，例如NiP，NiB，AuSn，Pt-Rh等。使用Pd作为种子层对于铜背面金属层特别有用，因为Pd层还用作扩散阻挡层以防止Cu原子进入半导体晶片。

5. 发明申请

US20130207266A1 Copper Interconnect for III-V Compound Semiconductor Devices 审中-公开
标题翻译：铜互连用于III-V复合半导体器件
公开(公告)号：US20130207266A1
公开(公告)日：2013-08-15
申请号：US13533303
申请日：2012-06-26
申请人： Chang-Hwang Hua , Wen Chu
发明人： Chang-Hwang Hua , Wen Chu
IPC分类号： H01L23/535
CPC分类号： H01L23/53238 , H01L27/0605 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a copper interconnect for III-V compound semiconductor devices, which comprises a metal contact layer and a copper-containing metal layer, in which the metal contact layer is formed of a material selected from a group consisting of Ti/Pd/Cu, Ti/NiV/Cu, TiW/TiWN/TiW/Cu, TiW/TiWN/TiW/Au, TiW/Cu, and TiW/Au, and the copper-containing metal layer comprises a copper layer. The copper-containing metal layer further includes a metal protection layer covering on the copper layer to prevent the copper layer from oxidation. The metal protection layer is formed of Ni/Au, Ni/Pd/Au, NiV/Au, or solder.
摘要翻译：本发明提供了一种用于III-V族化合物半导体器件的铜互连，其包括金属接触层和含铜金属层，其中金属接触层由选自Ti / Pd / Cu，Ti / NiV / Cu，TiW / TiWN / TiW / Cu，TiW / TiWN / TiW / Au，TiW / Cu和TiW / Au，含铜金属层包含铜层。含铜金属层还包括覆盖在铜层上的金属保护层，以防止铜层氧化。金属保护层由Ni / Au，Ni / Pd / Au，NiV / Au或焊料形成。

6. 发明申请

US20130034959A1 ELECTROLESS PLATING APPARATUS AND METHOD 有权
标题翻译：电沉积设备和方法
公开(公告)号：US20130034959A1
公开(公告)日：2013-02-07
申请号：US13196179
申请日：2011-08-02
申请人： Jason CHEN , Nakano Liu , Winson Shao , Wen Chu , Chang-Hwang Hua
发明人： Jason CHEN , Nakano Liu , Winson Shao , Wen Chu , Chang-Hwang Hua
IPC分类号： H01L21/3205 , B05C11/10 , B05C11/00
CPC分类号： H01L21/288 , C23C18/1619 , C23C18/1666 , C23C18/1669 , H01L21/76843
摘要： An electroless plating apparatus and method designed specifically for plating at least one semiconductor wafer are disclosed. The apparatus comprises a container, a wafer holder, an electrolyte supplying unit, and an ultrasonic-vibration unit. The container is provided with at least an inlet and used for containing electrolyte. The wafer holder is provided within the container. The electrolyte supplying unit is used to supply the electrolyte into the container via the inlet. The ultrasonic-vibration unit consisting of at least one frequency ultrasonic transducer is disposed in the container for producing a uniform flow of electrolyte in the container. Thereby, the wafers can be uniformly plated, especially for wafers with fine via-holes or trench structures.
摘要翻译：公开了专门用于电镀至少一个半导体晶片的化学镀设备和方法。该装置包括容器，晶片保持器，电解质供给单元和超声波振动单元。容器设有至少一个入口，用于容纳电解液。晶片保持器设置在容器内。电解质供给单元用于经由入口将电解质供给到容器中。由至少一个频率超声波换能器组成的超声波振动单元设置在容器中，用于在容器中产生均匀的电解液流。因此，可以均匀地镀覆晶片，特别是对于具有精细通孔或沟槽结构的晶片。

7. 发明授权

US5288660A Method for forming self-aligned t-shaped transistor electrode 失效
标题翻译：用于形成自对准t形晶体管电极的方法
公开(公告)号：US5288660A
公开(公告)日：1994-02-22
申请号：US11998
申请日：1993-02-01
申请人： Chang-Hwang Hua , Simon S. Chan , Ding-Yuan Day
发明人： Chang-Hwang Hua , Simon S. Chan , Ding-Yuan Day
IPC分类号： H01L21/027 , H01L21/768 , H01L21/283 , H01L21/312
CPC分类号： H01L21/76802 , H01L21/0274
摘要： A T-shaped electrode is formed on a semiconductor substrate by first forming a dielectric film on the substrate. A first layer of photoresist is applied on the upper surface of the dielectric film, and a second layer of photoresist is applied over the first layer of photoresist. The first and second layers of photoresist have different optical properties, requiring different wavelengths of ultraviolet for exposure before developing. Portions of the first and second photoresist layers and the dielectric film are selectively removed by photolithographic techniques with one masking step for forming an opening to the substrate. The first and second photoresist layers adjacent to the opening are ion etched to expose the upper surface of the dielectric film adjacent to the opening. A portion of the first photoresist layer adjacent to the opening is removed to undercut the second photoresist layer. Metal is deposited in the opening and on the exposed upper surface of the dielectric film to form a T-shaped electrode. The first and second photoresist layers are then removed, thereby also removing metal deposited on top of the second layer of photoresist.
摘要翻译：首先在基板上形成电介质膜，在半导体基板上形成T字形电极。在电介质膜的上表面上施加第一层光致抗蚀剂，在第一层光致抗蚀剂上施加第二层光致抗蚀剂。第一层和第二层光致抗蚀剂具有不同的光学性质，在显影之前需要不同波长的紫外线进行曝光。通过光刻技术选择性地去除第一和第二光致抗蚀剂层和电介质膜的部分，其中一个掩模步骤用于形成对该基底的开口。邻近开口的第一和第二光致抗蚀剂层被离子蚀刻以暴露与开口相邻的电介质膜的上表面。去除与开口相邻的第一光致抗蚀剂层的一部分以切割第二光致抗蚀剂层。金属沉积在介质膜的开口和暴露的上表面上以形成T形电极。然后去除第一和第二光致抗蚀剂层，从而也去除沉积在第二层光致抗蚀剂上的金属。

8. 发明授权

US5127984A Rapid wafer thinning process 失效
标题翻译：快速晶圆薄化工艺
公开(公告)号：US5127984A
公开(公告)日：1992-07-07
申请号：US694904
申请日：1991-05-02
申请人： Chang-Hwang Hua , Ding Y. S. Day
发明人： Chang-Hwang Hua , Ding Y. S. Day
IPC分类号： H01L21/306
CPC分类号： H01L21/30612
摘要： A method for thinning a Gallium Arsenide (GaAs) layer on the backside of a wafer substrate is provided. The method involves spraying an etchant solution including NH.sub.4 OH and H.sub.2 O.sub.2, preferably in a 1:4 ratio, onto the GaAs layer as the wafer is rotated at approximately 2000 rpm. The etchant is sprayed through a plurality of spray nozzles. The process is capable of thinning a GaAs layer by about 500 .mu.m in approximately 14 to 18 minutes, depending on the etchant temperature and composition.
摘要翻译：提供了一种用于在晶片衬底的背面上稀释砷化镓（GaAs）层的方法。该方法包括当晶片以大约2000rpm旋转时，将包括NH 4 OH和H 2 O 2的蚀刻剂溶液，优选以1:4的比例喷涂到GaAs层上。蚀刻剂通过多个喷嘴喷射。该方法能够在约14至18分钟内使GaAs层减薄约500μm，这取决于蚀刻剂的温度和组成。

9. 发明授权

US4842699A Method of selective via-hole and heat sink plating using a metal mask 失效
标题翻译：使用金属掩模的选择性通孔和散热电镀方法
公开(公告)号：US4842699A
公开(公告)日：1989-06-27
申请号：US192199
申请日：1988-05-10
申请人： Chang-Hwang Hua , Ding-Yuan S. Day , Simon S. Chan
发明人： Chang-Hwang Hua , Ding-Yuan S. Day , Simon S. Chan
IPC分类号： C25D5/02 , H01L21/768 , H01L23/48
CPC分类号： C25D5/022 , H01L21/76898 , H01L23/481 , H01L2924/0002
摘要： A method for simultaneous selective plating of viaholes and heat sinks associated with a semiconductor wafer using a metal mask and comprising the steps of:(a) coating a first side of the wafer with an insulating layer to prevent electroplating on this first side;(b) patterning on a second side of the wafer, opposite to the first side, a metal mask for defining the areas where plating should not occur;(c) forming via-holes through said wafer;(d) depositing a thin conductive film to coat the bottom and walls of the via-holes as well as areas of the second side of the wafer not covered by the metal mask; and(e) electrolytically plating the resulting wafer while ultrasonically agitating the electrolyte if necessary to ensure sufficient electrolyte transport into the via-holes for uniform plating.
摘要翻译：一种使用金属掩模同时选择性地电镀与半导体晶片相关的通孔和散热器的方法，包括以下步骤：（a）用绝缘层涂覆晶片的第一侧以防止在该第一侧上的电镀; （b）在晶片的与第一侧相对的第二面上图案化，用于限定不应发生电镀的区域的金属掩模; （c）通过所述晶片形成通孔; （d）沉积薄的导电膜以覆盖通孔的底部和壁以及未被金属掩模覆盖的晶片的第二面的区域; 和（e）如果需要的话，对所得的晶片进行电解电镀，同时超声波地搅动电解质，以确保足够的电解质输送到通孔中用于均匀的电镀。

10. 发明申请

US20130277845A1 STRUCTURE OF BACKSIDE COPPER METALLIZATION FOR SEMICONDUCTOR DEVICES AND A FABRICATION METHOD THEREOF 审中-公开
标题翻译：用于半导体器件的后置铜金属化的结构及其制造方法
公开(公告)号：US20130277845A1
公开(公告)日：2013-10-24
申请号：US13555793
申请日：2012-07-23
申请人： Jason CHEN , Chang-Hwang HUA , Wen CHU
发明人： Jason CHEN , Chang-Hwang HUA , Wen CHU
IPC分类号： H01L23/48 , H01L21/283
CPC分类号： H01L23/481 , H01L21/76898 , H01L2924/0002 , H01L2924/00
摘要： An improved structure of backside copper metallization for semiconductor devices and a fabrication method thereof, in which the improved structure comprises sequentially from top to bottom an active layer, a substrate, a backside metal seed layer, at least one thermal expansion buffer layer, a backside metal layer, and at least one oxidation resistant layer, in which the backside metal seed layer is formed of Pd, and the thermal expansion coefficient of the thermal expansion buffer layer is in the range between the thermal expansion coefficients of the backside metal seed layer and of the backside metal layer. The semiconductor chip using the structure provided by the present invention can sustain high-temperature operations.
摘要翻译：用于半导体器件的背面铜金属化的改进结构及其制造方法，其中改进的结构从上到下依次包括有源层，衬底，背面金属籽晶层，至少一个热膨胀缓冲层，背面金属层和至少一层抗氧化层，其中背面金属种子层由Pd形成，热膨胀缓冲层的热膨胀系数在背面金属种子层和的背面金属层。使用由本发明提供的结构的半导体芯片可以维持高温操作。

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