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1. 发明申请

US20090116298A1 APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE EVALUATION 失效
标题翻译：用于实现SRAM单元写入性能评估的设备
公开(公告)号：US20090116298A1
公开(公告)日：2009-05-07
申请号：US12351920
申请日：2009-01-12
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译： SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

2. 发明授权

US07768851B2 Apparatus for implementing SRAM cell write performance evaluation 失效
标题翻译：用于实现SRAM单元写入性能评估的装置
公开(公告)号：US07768851B2
公开(公告)日：2010-08-03
申请号：US12351920
申请日：2009-01-12
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译： SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

3. 发明授权

US07788554B2 Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluation 失效
标题翻译：体现在用于实现SRAM单元写入性能评估的机器可读介质中的设计结构
公开(公告)号：US07788554B2
公开(公告)日：2010-08-31
申请号：US11873173
申请日：2007-10-16
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A design structure embodied in a machine readable medium for implementing static random access memory (SRAM) cell write performance evaluation is provided. A SRAM core includes each wordline connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译：提供了体现在用于实现静态随机存取存储器（SRAM）单元写入性能评估的机器可读介质中的设计结构。 SRAM内核包括只连接到一个位列的每个字线。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

4. 发明授权

US07505340B1 Method for implementing SRAM cell write performance evaluation 失效
标题翻译：实现SRAM单元写入性能评估的方法
公开(公告)号：US07505340B1
公开(公告)日：2009-03-17
申请号：US11845866
申请日：2007-08-28
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A method implements static random access memory (SRAM) cell write performance evaluation. A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译：一种方法实现了静态随机存取存储器（SRAM）单元写入性能评估。 SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。控制信号被施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

5. 发明申请

US20090063912A1 Method and Apparatus for Implementing SRAM Cell Write Performance Evaluation 失效
标题翻译：实现SRAM单元写入性能评估的方法和装置
公开(公告)号：US20090063912A1
公开(公告)日：2009-03-05
申请号：US11873173
申请日：2007-10-16
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C29/08
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A method and apparatus for implementing static random access memory (SRAM) cell write performance evaluation, and a design structure on which the subject circuit resides are provided. ASRAM core includes each wordline connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译：一种用于实现静态随机存取存储器（SRAM）单元写入性能评估的方法和装置，以及设置有主题电路所在的设计结构。 ASRAM内核包括只连接到一个位列的每个字线。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

6. 发明申请

US20090059697A1 METHOD AND APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE EVALUATION 失效
标题翻译：用于实现SRAM单元写性能评估的方法和装置
公开(公告)号：US20090059697A1
公开(公告)日：2009-03-05
申请号：US11845866
申请日：2007-08-28
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译： SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。控制信号被施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

7. 发明申请

US20100118621A1 Implementing Variation Tolerant Memory Array Signal Timing 审中-公开
标题翻译：实现变化容差存储器阵列信号时序
公开(公告)号：US20100118621A1
公开(公告)日：2010-05-13
申请号：US12266580
申请日：2008-11-07
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/08 , G11C7/222
摘要： A method and signal timing adjustment circuit for implementing variation tolerant memory array signal timing, and a design structure on which the subject circuit resides are provided. A logic circuit generates a first delay signal based upon logic devices forming the logic circuit. A memory cell circuit receives the first delay signal and generates control signals responsive to the first delay signal and based upon memory cell devices forming the memory cell circuit. A programmable logic delay circuit receives the control signals and generates a timing adjustment signal.
摘要翻译：一种用于实现变形容限存储器阵列信号定时的方法和信号定时调整电路，以及设置有被摄体电路的设计结构。逻辑电路基于形成逻辑电路的逻辑器件产生第一延迟信号。存储单元电路接收第一延迟信号并且响应于第一延迟信号并且基于形成存储器单元电路的存储单元装置产生控制信号。可编程逻辑延迟电路接收控制信号并产生定时调整信号。

8. 发明授权

US08467230B2 Data security for dynamic random access memory using body bias to clear data at power-up 有权
标题翻译：使用身体偏倚的动态随机存取存储器的数据安全性，以在上电时清除数据
公开(公告)号：US08467230B2
公开(公告)日：2013-06-18
申请号：US12898924
申请日：2010-10-06
申请人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Michael Launsbach , Daniel Mark Nelson
发明人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Michael Launsbach , Daniel Mark Nelson
IPC分类号： G11C11/24
CPC分类号： G11C7/24 , G11C5/145 , G11C7/20 , G11C11/4072 , G11C11/4078
摘要： A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.
摘要翻译：电路和方法在上电时擦除存储在DRAM芯片中的所有数据，以提高数据安全性。通过增加单元的体电压同时接通DRAM存储单元的晶体管，可以擦除所有的DRAM存储单元。在示例电路中，通过由对存储器单元的p阱施加电压的上电复位（POR）信号控制的电荷泵增加体电压。向p阱施加的电压降低了电池的阈值电压，使得存储器单元的NFET晶体管将导通。当所有设备都打开时，存储在存储单元中的数据将被擦除，因为连接到通用位线的所有单元的电压合并为单个值。

9. 发明授权

US08159260B1 Delay chain burn-in for increased repeatability of physically unclonable functions 失效
标题翻译：延迟链老化可增加物理不可克隆功能的重复性
公开(公告)号：US08159260B1
公开(公告)日：2012-04-17
申请号：US12898044
申请日：2010-10-05
申请人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： H03K19/00 , G06F11/30 , G06F13/00
CPC分类号： G06F7/588 , H04L9/0866
摘要： A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.
摘要翻译：电路和方法通过在芯片烧录期间通过两个延迟链增强信号延迟的变化来增加物理上不可检测的功能（PUF）的重复性。老化电路在老化过程中将两个延迟链的输入保持相反的随机值。延迟链中所有在输入端具有低电平值的PFET将以更高的导通电压进行烧录。由于在两个延迟链中受影响的PFET在老化期间被相反的转变驱动，所以两个延迟链中的延迟组件的交替组合受老化周期的影响。在正常操作下，两个延迟链看到相同的输入，所以只有一个链延迟增加，以实现两个延迟路径的统计上可靠的差异，从而增加了PUF电路的整体重复性。

10. 发明申请

US20120081143A1 DELAY CHAIN BURN-IN FOR INCREASED REPEATABILITY OF PHYSICALLY UNCLONABLE FUNCTIONS 失效
标题翻译：延迟链燃烧以增加物理不可靠功能的重复性
公开(公告)号：US20120081143A1
公开(公告)日：2012-04-05
申请号：US12898044
申请日：2010-10-05
申请人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： H03K19/00
CPC分类号： G06F7/588 , H04L9/0866
摘要： A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.
摘要翻译：电路和方法通过在芯片烧录期间通过两个延迟链增强信号延迟的变化来增加物理上不可检测的功能（PUF）的重复性。老化电路在老化过程中将两个延迟链的输入保持相反的随机值。延迟链中所有在输入端具有低电平值的PFET将以更高的导通电压进行烧录。由于在两个延迟链中受影响的PFET在老化期间被相反的转变驱动，所以两个延迟链中的延迟组件的交替组合受老化周期的影响。在正常操作下，两个延迟链看到相同的输入，所以只有一个链延迟增加，以实现两个延迟路径的统计上可靠的差异，从而增加了PUF电路的整体重复性。

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