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1. 发明授权

US07684263B2 Method and circuit for implementing enhanced SRAM write and read performance ring oscillator 失效
标题翻译：实现增强型SRAM写和读性能环形振荡器的方法和电路
公开(公告)号：US07684263B2
公开(公告)日：2010-03-23
申请号：US12015806
申请日：2008-01-17
申请人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Travis Reynold Hebig
发明人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Travis Reynold Hebig
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A method and circuit for implementing an enhanced static random access memory (SRAM) read and write performance ring oscillator, and a design structure on which the subject circuit resides are provided. A plurality of SRAM base blocks is connected together in a chain. Each of the plurality of SRAM base blocks includes a SRAM cell, such as an eight-transistor (8T) static random access memory (SRAM) cell, and a local evaluation block coupled to the SRAM cell. The SRAM cell includes independent left wordline input and right wordline input. The SRAM cell includes a read wordline connected high, and a true and complement write bitline pair connected low. In the local evaluation circuit, one input of a NAND gate receiving the read bitline input is connected high. A control signal is combined with an inverted feedback signal to start and stop the ring oscillator.
摘要翻译：一种用于实现增强型静态随机存取存储器（SRAM）读写性能环形振荡器的方法和电路，以及设置有被摄体电路所在的设计结构。多个SRAM基块在链中连接在一起。多个SRAM基块中的每一个包括诸如八晶体管（8T）静态随机存取存储器（SRAM）单元的SRAM单元，以及耦合到SRAM单元的局部评估块。 SRAM单元包括独立的左字线输入和右字线输入。 SRAM单元包括一个连接到高电平的读字字线和一个连接低电平的真写补码写位线对。在本地评估电路中，接收读取位线输入的NAND门的一个输入被连接得很高。控制信号与反相反馈信号相结合，以启动和停止环形振荡器。

2. 发明授权

US07835176B2 Implementing enhanced dual mode SRAM performance screen ring oscillator 有权
标题翻译：实现增强型双模SRAM性能屏环振荡器
公开(公告)号：US07835176B2
公开(公告)日：2010-11-16
申请号：US12360230
申请日：2009-01-27
申请人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Travis Reynold Hebig
发明人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Travis Reynold Hebig
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C7/1045 , G11C8/18 , G11C11/412 , G11C11/413
摘要： A method and circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO), and a design structure on which the subject circuit resides are provided. The dual-mode SRAM PSRO includes a plurality of SRAM base blocks connected together in a chain. Each of the plurality of SRAM base blocks includes an eight-transistor (8T) SRAM cell, a local evaluation circuit and a logic function coupled to the SRAM cell. The eight-transistor (8T) static random access memory (SRAM) cell is an unmodified 8T SRAM cell. The dual-mode SRAM PSRO includes one mode of operation, where the output frequency is determined by write-through performance of the 8T SRAM cell; and another mode of operation, where the output frequency is determined by read performance of the 8T SRAM cell.
摘要翻译：一种用于实现增强型双模式静态随机存取存储器（SRAM）性能屏幕环形振荡器（PSRO）的方法和电路，以及设置有被摄体电路的设计结构。双模SRAM PSRO包括连接在一起的多个SRAM基块。多个SRAM基块中的每一个包括八晶体管（8T）SRAM单元，局部评估电路和耦合到SRAM单元的逻辑功能。八晶体管（8T）静态随机存取存储器（SRAM）单元是未修改的8T SRAM单元。双模SRAM PSRO包括一种工作模式，其中输出频率由8T SRAM单元的直写性能决定; 和另一种操作模式，其中输出频率由8T SRAM单元的读取性能决定。

3. 发明申请

US20100188888A1 Implementing Enhanced Dual Mode SRAM Performance Screen Ring Oscillator 有权
标题翻译：实现增强型双模SRAM性能屏幕环形振荡器
公开(公告)号：US20100188888A1
公开(公告)日：2010-07-29
申请号：US12360230
申请日：2009-01-27
申请人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Travis Reynold Hebig
发明人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Travis Reynold Hebig
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C7/1045 , G11C8/18 , G11C11/412 , G11C11/413
摘要： A method and circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO), and a design structure on which the subject circuit resides are provided. The dual-mode SRAM PSRO includes a plurality of SRAM base blocks connected together in a chain. Each of the plurality of SRAM base blocks includes an eight-transistor (8T) SRAM cell, a local evaluation circuit and a logic function coupled to the SRAM cell. The eight-transistor (8T) static random access memory (SRAM) cell is an unmodified 8T SRAM cell. The dual-mode SRAM PSRO includes one mode of operation, where the output frequency is determined by write-through performance of the 8T SRAM cell; and another mode of operation, where the output frequency is determined by read performance of the 8T SRAM cell.
摘要翻译：一种用于实现增强型双模式静态随机存取存储器（SRAM）性能屏幕环形振荡器（PSRO）的方法和电路，以及设置有被摄体电路的设计结构。双模SRAM PSRO包括连接在一起的多个SRAM基块。多个SRAM基块中的每一个包括八晶体管（8T）SRAM单元，局部评估电路和耦合到SRAM单元的逻辑功能。八晶体管（8T）静态随机存取存储器（SRAM）单元是未修改的8T SRAM单元。双模SRAM PSRO包括一种工作模式，其中输出频率由8T SRAM单元的直写性能决定; 和另一种操作模式，其中输出频率由8T SRAM单元的读取性能决定。

4. 发明申请

US20090185435A1 Method and Circuit for Implementing Enhanced SRAM Write and Read Performance Ring Oscillator 失效
标题翻译：实现增强型SRAM写和读性能环形振荡器的方法和电路
公开(公告)号：US20090185435A1
公开(公告)日：2009-07-23
申请号：US12015806
申请日：2008-01-17
申请人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Travis Reynold Hebig
发明人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Travis Reynold Hebig
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A method and circuit for implementing an enhanced static random access memory (SRAM) read and write performance ring oscillator, and a design structure on which the subject circuit resides are provided. A plurality of SRAM base blocks is connected together in a chain. Each of the plurality of SRAM base blocks includes a SRAM cell, such as an eight-transistor (8T) static random access memory (SRAM) cell, and a local evaluation block coupled to the SRAM cell. The SRAM cell includes independent left wordline input and right wordline input. The SRAM cell includes a read wordline connected high, and a true and complement write bitline pair connected low. In the local evaluation circuit, one input of a NAND gate receiving the read bitline input is connected high. A control signal is combined with an inverted feedback signal to start and stop the ring oscillator.
摘要翻译：一种用于实现增强型静态随机存取存储器（SRAM）读写性能环形振荡器的方法和电路，以及设置有被摄体电路所在的设计结构。多个SRAM基块在链中连接在一起。多个SRAM基块中的每一个包括诸如八晶体管（8T）静态随机存取存储器（SRAM）单元的SRAM单元，以及耦合到SRAM单元的局部评估块。 SRAM单元包括独立的左字线输入和右字线输入。 SRAM单元包括一个连接到高电平的读字字线和一个连接低电平的真写补码写位线对。在本地评估电路中，接收读取位线输入的NAND门的一个输入被连接得很高。控制信号与反相反馈信号相结合，以启动和停止环形振荡器。

5. 发明申请

US20090027945A1 Method and Apparatus for Implementing Enhanced SRAM Read Performance Sort Ring Oscillator (PSRO) 有权
标题翻译：实现增强型SRAM读取性能排序环形振荡器（PSRO）的方法和装置
公开(公告)号：US20090027945A1
公开(公告)日：2009-01-29
申请号：US11873534
申请日：2007-10-17
申请人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
发明人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject circuit resides is provided. A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.
摘要翻译：一种包括静态随机存取存储器（SRAM）单元的方法和装置实现增强的SRAM读取性能排序环形振荡器（PSRO），以及设置有被摄体电路所在的设计结构。一对并联反极性连接的反相器定义了静态锁存器或交叉耦合存储器单元。 SRAM单元包括独立的左和右字线，为用于访问存储单元的一对存取晶体管提供相应的栅极输入。 SRAM单元包括到静态锁存器的一侧的电压供应连接。例如，静态锁存器的补码侧连接到电源。多个SRAM单元组装在一起以形成SRAM基块。多个SRAM基块被连接在一起以形成SRAM读取PSRO。

6. 发明授权

US07480170B1 Method and apparatus for implementing enhanced SRAM read performance sort ring oscillator (PSRO) 有权
标题翻译：实现增强型SRAM读取性能排序环形振荡器（PSRO）的方法和装置
公开(公告)号：US07480170B1
公开(公告)日：2009-01-20
申请号：US11782808
申请日：2007-07-25
申请人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
发明人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
IPC分类号： G11C11/40
CPC分类号： G11C11/413 , G11C11/41 , G11C11/419 , G11C2029/0403
摘要： A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO). A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.
摘要翻译：包括静态随机存取存储器（SRAM）单元的方法和装置实现增强型SRAM读取性能排序环形振荡器（PSRO）。一对并联反极性连接的反相器定义了静态锁存器或交叉耦合存储器单元。 SRAM单元包括独立的左和右字线，为用于访问存储单元的一对存取晶体管提供相应的栅极输入。 SRAM单元包括到静态锁存器的一侧的电压供应连接。例如，静态锁存器的补码侧连接到电源。多个SRAM单元组装在一起以形成SRAM基块。多个SRAM基块被连接在一起以形成SRAM读取PSRO。

7. 发明授权

US07609542B2 Implementing enhanced SRAM read performance sort ring oscillator (PSRO) 有权
标题翻译：实现增强型SRAM读取性能排序环形振荡器（PSRO）
公开(公告)号：US07609542B2
公开(公告)日：2009-10-27
申请号：US11873534
申请日：2007-10-17
申请人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
发明人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
IPC分类号： G11C11/40
CPC分类号： G11C11/413
摘要： A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject circuit resides is provided. A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.
摘要翻译：一种包括静态随机存取存储器（SRAM）单元的方法和装置实现增强的SRAM读取性能排序环形振荡器（PSRO），以及设置有被摄体电路所在的设计结构。一对并联反极性连接的反相器定义了静态锁存器或交叉耦合存储器单元。 SRAM单元包括独立的左和右字线，为用于访问存储单元的一对存取晶体管提供相应的栅极输入。 SRAM单元包括到静态锁存器的一侧的电压供应连接。例如，静态锁存器的补码侧连接到电源。多个SRAM单元组装在一起以形成SRAM基块。多个SRAM基块被连接在一起以形成SRAM读取PSRO。

8. 发明申请

US20090027946A1 METHOD AND APPARATUS FOR IMPLEMENTING ENHANCED SRAM READ PERFORMANCE SORT RING OSCILLATOR (PSRO) 有权
标题翻译：实现增强SRAM读取性能分析振荡器（PSRO）的方法和设备
公开(公告)号：US20090027946A1
公开(公告)日：2009-01-29
申请号：US11782808
申请日：2007-07-25
申请人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
发明人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C11/41 , G11C11/419 , G11C2029/0403
摘要： A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO). A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.
摘要翻译：包括静态随机存取存储器（SRAM）单元的方法和装置实现增强型SRAM读取性能排序环形振荡器（PSRO）。一对并联反极性连接的反相器定义了静态锁存器或交叉耦合存储器单元。 SRAM单元包括独立的左和右字线，为用于访问存储单元的一对存取晶体管提供相应的栅极输入。 SRAM单元包括到静态锁存器的一侧的电压供应连接。例如，静态锁存器的补码侧连接到电源。多个SRAM单元组装在一起以形成SRAM基块。多个SRAM基块被连接在一起以形成SRAM读取PSRO。

9. 发明申请

US20060087873A1 METHOD AND SUM ADDRESSED CELL ENCODER FOR ENHANCED COMPARE AND SEARCH TIMING FOR CAM COMPARE 有权
标题翻译：用于CAM比较的增强比较和搜索时序的方法和寻址小区编码器
公开(公告)号：US20060087873A1
公开(公告)日：2006-04-27
申请号：US10970522
申请日：2004-10-21
申请人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
发明人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A method and a sum addressed content-addressable memory (CAM) compare are provided for implementing an enhanced sum address compare function. True and compliment bit signals applied to the CAM compare are encoded by combining respective ones of the applied true and compliment bit signals. Then the encoded true and compliment bit signals are applied to a critical path dynamic compare circuit. An encoder apparatus encodes true and compliment bit signals that then are applied to the dynamic compare circuit in the critical path.
摘要翻译：提供了一种方法和和寻址内容寻址存储器（CAM）比较，用于实现增强的和地址比较功能。应用于CAM比较的真实和补码比特信号通过组合所应用的真实和补码比特信号中的相应的一些来进行编码。然后将编码的真实和补码位信号应用于关键路径动态比较电路。编码器装置对真实和补码比特信号进行编码，然后将其应用于关键路径中的动态比较电路。

10. 发明授权

US07035127B1 Method and sum addressed cell encoder for enhanced compare and search timing for CAM compare 有权
标题翻译：方法和和寻址单元编码器，用于CAM比较的增强比较和搜索时序
公开(公告)号：US07035127B1
公开(公告)日：2006-04-25
申请号：US10970522
申请日：2004-10-21
申请人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
发明人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A method and a sum addressed content-addressable memory (CAM) compare are provided for implementing an enhanced sum address compare function. True and compliment bit signals applied to the CAM compare are encoded by combining respective ones of the applied true and compliment bit signals. Then the encoded true and compliment bit signals are applied to a critical path dynamic compare circuit. An encoder apparatus encodes true and compliment bit signals that then are applied to the dynamic compare circuit in the critical path.
摘要翻译：提供了一种方法和和寻址内容寻址存储器（CAM）比较，用于实现增强的和地址比较功能。应用于CAM比较的真实和补码比特信号通过组合所应用的真实和补码比特信号中的相应的一些来进行编码。然后将编码的真实和补码位信号应用于关键路径动态比较电路。编码器装置对真实和补码比特信号进行编码，然后将其应用于关键路径中的动态比较电路。

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