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1. 发明申请

WO2016048336A1 SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：半导体器件的选择栅极间隔
公开(公告)号：WO2016048336A1
公开(公告)日：2016-03-31
申请号：PCT/US2014/057585
申请日：2014-09-26
申请人： INTEL CORPORATION , CLENDENNING, Scott B. , LIAO, Szuya S. , GSTREIN, Florian , HOURANI, Rami , ROMERO, Patricio E. , KLOSTER, Grant M. , MITAN, Martin M.
发明人： CLENDENNING, Scott B. , LIAO, Szuya S. , GSTREIN, Florian , HOURANI, Rami , ROMERO, Patricio E. , KLOSTER, Grant M. , MITAN, Martin M.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0673 , H01L21/265 , H01L21/28247 , H01L29/42364 , H01L29/4983 , H01L29/51 , H01L29/66439 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.
摘要翻译：讨论了与形成用于半导体器件和晶体管结构的选择性栅极间隔物以及使用这种技术形成的器件有关的技术。这样的技术包括在半导体鳍片上形成阻挡材料，在阻挡材料的一部分上设置具有与阻挡材料不同的表面化学性质的栅极，在栅极上形成选择性共形层，而不是在阻挡材料的一部分上，以及去除封闭材料的暴露部分。

2. 发明申请

WO2016099570A1 SELECTIVE DEPOSITION UTILIZING SACRIFICIAL BLOCKING LAYERS FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：选择性沉积利用半导体器件的极化阻挡层
公开(公告)号：WO2016099570A1
公开(公告)日：2016-06-23
申请号：PCT/US2014/071717
申请日：2014-12-19
申请人： INTEL CORPORATION , KLOSTER, Grant , CLENDENNING, Scott B. , HOURANI, Rami , LIAO, Szuya S. , ROMERO, Patricio E. , GSTREIN, Florian
发明人： KLOSTER, Grant , CLENDENNING, Scott B. , HOURANI, Rami , LIAO, Szuya S. , ROMERO, Patricio E. , GSTREIN, Florian
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7851 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28194 , H01L21/3105 , H01L21/31058 , H01L21/31133 , H01L21/32 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L29/0649 , H01L29/0673 , H01L29/42368 , H01L29/42392 , H01L29/517 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/786
摘要： Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.
摘要翻译：公开了在半导体结构上选择性地沉积高K栅极电介质的方法。该方法包括提供设置在半导体衬底之上的半导体结构。半导体结构设置在隔离侧壁旁边。牺牲阻挡层然后选择性地沉积在隔离侧壁上，而不是半导体结构上。此后，高K栅极电介质沉积在半导体结构上，但不沉积在牺牲阻挡层上。牺牲阻挡层的性质防止氧化物材料在其表面上的沉积。然后进行热处理以去除牺牲阻挡层，从而仅在半导体结构上形成高K栅极电介质。

3. 发明申请

WO2015047345A1 FORMING LAYERS OF MATERIALS OVER SMALL REGIONS BY SELECTIVE CHEMICAL REACTION INCLUDING LIMITING ENCROACHMENT OF THE LAYERS OVER ADJACENT REGIONS 审中-公开
标题翻译：通过选择性化学反应在小区域形成材料层，包括在相邻区域限制层的加强
公开(公告)号：WO2015047345A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/062456
申请日：2013-09-27
申请人： INTEL CORPORATION , BRISTOL, Robert L. , BLACKWELL, James M. , CLENDENNING, Scott B. , GSTREIN, Florian , HAN, Eungnak , KLOSTER, Grant M. , ROBERTS, Jeanette M. , ROMERO, Patricio E. , HOURANI, Rami
发明人： BRISTOL, Robert L. , BLACKWELL, James M. , CLENDENNING, Scott B. , GSTREIN, Florian , HAN, Eungnak , KLOSTER, Grant M. , ROBERTS, Jeanette M. , ROMERO, Patricio E. , HOURANI, Rami
IPC分类号： H01L21/31
CPC分类号： H01L23/528 , H01L21/28562 , H01L21/288 , H01L21/3105 , H01L21/31058 , H01L21/311 , H01L21/32 , H01L21/32051 , H01L21/321 , H01L21/76801 , H01L21/76816 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76877 , H01L21/76897 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.
摘要翻译：一个方面的方法包括通过分开地通过选择性化学反应分别形成第一多个较薄层中的每一个，在具有第一表面材料的第一区域上形成第一材料的第一较厚层。该方法还包括限制在与第一区域相邻的第二区域上的第一多个较薄层中的每一个的侵入。在第二区域上形成第二较厚的第二材料层，其具有不同于第一表面材料的第二表面材料。

4. 发明申请

WO2015147843A1 PRECURSOR AND PROCESS DESIGN FOR PHOTO-ASSISTED METAL ATOMIC LAYER DEPOSITION (ALD) AND CHEMICAL VAPOR DEPOSITION (CVD) 审中-公开
标题翻译：辅助金属原子层沉积（ALD）和化学气相沉积（CVD）的前驱物和工艺设计
公开(公告)号：WO2015147843A1
公开(公告)日：2015-10-01
申请号：PCT/US2014/032073
申请日：2014-03-27
申请人： INTEL CORPORATION , BLACKWELL, James M. , ROMERO, Patricio E. , CLENDENNING, Scott B. , KLOSTER, Grant M. , GSTREIN, Florian , SIMKA, Harsono S. , ZIMMERMAN, Paul A. , BRISTOL, Robert L.
发明人： BLACKWELL, James M. , ROMERO, Patricio E. , CLENDENNING, Scott B. , KLOSTER, Grant M. , GSTREIN, Florian , SIMKA, Harsono S. , ZIMMERMAN, Paul A. , BRISTOL, Robert L.
IPC分类号： C23C16/455 , C23C16/52 , H01L21/285
CPC分类号： C23C16/45553 , C23C16/18 , C23C16/482 , H01L21/0337 , H01L21/28556 , H01L21/28562 , H01L21/76816 , H01L21/76879 , H01L21/76897 , H01L29/66795
摘要： Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.
摘要翻译：描述了光辅助金属原子层沉积（ALD）和化学气相沉积（CVD）的前体和工艺设计。在一个实例中，制造薄金属膜的方法包括将前体分子引入靠近基底上或表面的表面，每个前体分子具有被配体包围的一个或多个金属中心。该方法还涉及通过使用光辅助方法从前体分子解离配体而在表面上沉积金属层。

5. 发明申请

WO2019066825A1 PASSIVATION LAYER FOR GERMANIUM SUBSTRATE 审中-公开
公开(公告)号：WO2019066825A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/053843
申请日：2017-09-27
申请人： INTEL CORPORATION , ROMERO, Patricio E. , CLENDENNING, Scott B. , GSTREIN, Florian , TAN, Cen
发明人： ROMERO, Patricio E. , CLENDENNING, Scott B. , GSTREIN, Florian , TAN, Cen
IPC分类号： H01L21/02 , H01L29/78
摘要： Embodiments herein describe techniques for a semiconductor device including a Ge substrate. A passivation layer may be formed above the Ge substrate, where the passivation layer may include one or more molecular monolayers with atoms of one or more group 15 elements or group 16 elements. In addition, a low-k interlayer may be above the passivation layer, and a high-k interlayer may be above the low-k interlayer. Furthermore, a metal contact may be above the high-k interlayer. Other embodiments may be described and/or claimed.

6. 发明申请

WO2018009158A1 CONFORMAL FILMS INCLUDING METAL GALLIUM CARBIDE AND METAL INDIUM CARBIDE FOR DEVICE APPLICATIONS AND THEIR FABRICATION 审中-公开
标题翻译：包含金属镓碳化物和金属铟碳化物的器件适用于器件应用及其制造
公开(公告)号：WO2018009158A1
公开(公告)日：2018-01-11
申请号：PCT/US2016/040894
申请日：2016-07-02
申请人： INTEL CORPORATION , CLENDENNING, Scott B. , KIM, Kyoung H. , ROMERO, Patricio E.
发明人： CLENDENNING, Scott B. , KIM, Kyoung H. , ROMERO, Patricio E.
IPC分类号： H01L21/28 , H01L21/02 , H01L29/78
摘要： An apparatus including an integrated circuit device structure including a metal layer including a composition of General Formula I: M-Al m -X 1 n -X 2 p -C q -O r , wherein M includes a metal selected from one or more of titanium, zirconium, hafnium, tantalum, niobium and vanadium, wherein C includes carbon, wherein X 1 includes gallium, wherein X 2 includes indium, wherein m, n, p, q and r represent an atomic percent of an element in the metal layer that can be 0 percent, with the proviso that n and p cannot each be 0 percent. A method including introducing a first precursor including a metal halide into a chamber including an integrated circuit structure, introducing a second precursor of at least one of an organogallium compound and organoindium compound into the chamber; and depositing a metal including the metal cation of the halide and at least one of gallium and indium.
摘要翻译：一种包括集成电路器件结构的设备，所述集成电路器件结构包括包含通式I的组成的金属层：M-Al m -X 1 ^{1 其中M包括一个或多个取代基，其中M包括一个或一个以上的取代基，选自钛，锆，铪，钽，铌和钒中的一种或多种的金属，其中C包括碳，其中X 1包括镓，其中X 2包括铟，其中m，n，p，q和r表示金属层中元素的原子百分比，其可以为0％，条件是n和p不能各为0％。包括将包含金属卤化物的第一前体引入包括集成电路结构的腔室中，将有机镓化合物和有机铟化合物中的至少一种的第二前体引入腔室中; 并沉积包括卤化物的金属阳离子和镓和铟中的至少一种的金属。}

7. 发明申请

WO2018118086A1 GALLIUM-BASED CO-REACTANTS FOR FABRICATING METAL SILICIDE AND METAL GERMANIDE FILMS 审中-公开
公开(公告)号：WO2018118086A1
公开(公告)日：2018-06-28
申请号：PCT/US2016/068579
申请日：2016-12-23
申请人： INTEL CORPORATION , ROMERO, Patricio E. , CLENDENNING, Scott B. , TAN, Cen
发明人： ROMERO, Patricio E. , CLENDENNING, Scott B. , TAN, Cen
IPC分类号： H01L21/02 , C07F19/00
摘要： Gallium-based co-reactants for fabricating metal silicide and metal germanide films, and integrated circuit structures including such films, are described. In a first example, a discrete acyclic molecule includes a gallium-based moiety having a central gallium atom, and a silicon-based moiety having a central silicon atom. The central silicon atom of the silicon-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond. In a second example, a discrete acyclic molecule includes a gallium-based moiety having a central gallium atom, and a germanium-based moiety having a central germanium atom. The central germanium atom of the germanium-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond. In either case, a neutral Lewis basic ligand is bonded to the central gallium atom of the gallium-based moiety.

8. 发明申请

WO2013147856A1 PROCESS AND MATERIAL FOR PREVENTING DELETERIOUS EXPANSION OF HIGH ASPECT RATIO COPPER FILLED THROUGH SILICON VIAS (TSVS) 审中-公开
标题翻译：用于防止通过硅酮（TSVS）填充的高比例铜的去除膨胀的方法和材料
公开(公告)号：WO2013147856A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031486
申请日：2012-03-30
申请人： INTEL CORPORATION , ZIMMERMAN, Paul A. , CLENDENNING, Scott B. , ROMERO, Patricio E. , FISCHER, Paul B. , EDGEWORTH, Robert
发明人： ZIMMERMAN, Paul A. , CLENDENNING, Scott B. , ROMERO, Patricio E. , FISCHER, Paul B. , EDGEWORTH, Robert
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L21/02181 , H01L21/02189 , H01L21/02194 , H01L21/02205 , H01L21/0228 , H01L21/76831 , H01L21/76837 , H01L21/76841 , H01L21/76871 , H01L21/76879 , H01L23/481 , H01L23/60 , H01L23/642 , H01L25/0657 , H01L2224/16146 , H01L2225/06513 , H01L2225/06544
摘要： Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW2O8) or hafnium tungstate (HfW2O8). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages. Other embodiments which can employ techniques described herein will be apparent in light of this disclosure.
摘要翻译：公开了形成实现负热膨胀（NTE）材料如钨酸锆（ZrW2O8）或钨酸铪（HfW2O8）的穿硅通孔（TSV）的技术。在一些情况下，NTE材料设置在TSV的衬底和导电芯材之间，并且用于至少部分地抵消其间的热膨胀系数（CTE）失配，从而减少热诱导的应力和/或突出（泵送）导电芯材料。 NTE材料还可以防止导电芯材料的泄漏，电压击穿和/或扩散。此外，NTE材料可以降低高纵横比TSV中的径向应力。在一些情况下，本文公开的技术可以提高三维集成电路和/或其他三维封装中的TSV可靠性，增强三维集成和/或增强性能。根据本公开，可以使用本文描述的技术的其他实施例将是显而易见的。

9. 发明申请

WO2015195080A1 SELECTIVE DIFFUSION BARRIER BETWEEN METALS OF AN INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：集成电路设备金属之间的选择性扩散障碍
公开(公告)号：WO2015195080A1
公开(公告)日：2015-12-23
申请号：PCT/US2014/042568
申请日：2014-06-16
申请人： INTEL CORPORATION , ROBERTS, Jeanette A. , ROMERO, Patricio E. , CLENDENNING, Scott B. , JEZEWSKI, Christopher J. , CHEBIAM , Ramanan V.
发明人： ROBERTS, Jeanette A. , ROMERO, Patricio E. , CLENDENNING, Scott B. , JEZEWSKI, Christopher J. , CHEBIAM , Ramanan V.
IPC分类号： H01L21/38 , H01L21/31 , H01L21/205
CPC分类号： H01L23/53238 , H01L21/28556 , H01L21/28562 , H01L21/28568 , H01L21/288 , H01L21/3215 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L21/76855 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53209 , H01L24/17 , H01L25/105 , H01L2224/16225 , H01L2924/0002 , H01L2924/15311 , H05K1/181 , H05K2201/10734 , H01L2924/00
摘要： Embodiments of the present disclosure describe a selective diffusion barrier between metals of an integrated circuit (IC) device and associated techniques and configurations. In one embodiment, an apparatus includes a dielectric material, a first interconnect structure comprising a first metal disposed in the dielectric material, a second interconnect structure comprising a second metal disposed in the dielectric material and electrically coupled with the first interconnect structure and a diffusion barrier disposed at an interface between the first interconnect structure and the second interconnect structure, wherein the first metal and the second metal have a different chemical composition, material of the diffusion barrier and the second metal have a different chemical composition and material of the diffusion barrier is not disposed directly between the second metal and the dielectric material. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了集成电路（IC）器件的金属与相关联的技术和配置之间的选择性扩散阻挡层。在一个实施例中，一种装置包括电介质材料，第一互连结构，包括布置在电介质材料中的第一金属，第二互连结构，包括设置在电介质材料中并与第一互连结构电耦合的第二金属和扩散阻挡层设置在第一互连结构和第二互连结构之间的界面处，其中第一金属和第二金属具有不同的化学组成，扩散阻挡层和第二金属的材料具有不同的化学组成，并且扩散阻挡层的材料是不直接设置在第二金属和电介质材料之间。可以描述和/或要求保护其他实施例。

10. 发明申请

WO2013048417A1 ELECTROPOSITIVE METAL CONTAINING LAYERS FOR SEMICONDUCTOR APPLICATIONS 审中-公开
标题翻译：用于半导体应用的电镀金属包含层
公开(公告)号：WO2013048417A1
公开(公告)日：2013-04-04
申请号：PCT/US2011/054051
申请日：2011-09-29
申请人： INTEL CORPORATION , ROMERO, Patricio E. , CLENDENNING, Scott B.
发明人： ROMERO, Patricio E. , CLENDENNING, Scott B.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28556 , C23C16/30 , C23C16/42 , H01L21/28506 , H01L21/28562 , H01L21/28575 , H01L21/76843 , H01L21/76849 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53266 , H01L29/04 , H01L29/0673 , H01L29/16 , H01L29/161 , H01L29/201 , H01L29/42392 , H01L29/45 , H01L29/49 , H01L29/4916 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/51 , H01L29/518 , H01L29/66522 , H01L29/66568 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD (chemical vapor deposition) processes, layers comprising one or more electropositive metals, and semiconductor devices comprising layers comprising one or more electropositive metals. In embodiments of the invention, the layers are thin or ultrathin (films that are less than 100 Å thick) and or conformal films. Additionally provided are transistor devices, metal interconnects, and computing devices comprising metal layers comprising one or more electropositive metals.
摘要翻译：本发明的实施方案提供了通过ALD（原子层沉积）和/或CVD（化学气相沉积）工艺形成包含正电性金属的层的方法，包括一种或多种正电性金属的层以及包含一种或多种正电性金属的层的半导体器件。在本发明的实施方案中，这些层是薄的或超薄的（小于100埃的膜）和/或保形膜。另外提供的是晶体管器件，金属互连和包括包含一种或多种正电性金属的金属层的计算器件。

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