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1. 发明授权

US07429504B2 Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods 有权
标题翻译：异质IV族半导体衬底，形成在这种衬底上的集成电路及相关方法
公开(公告)号：US07429504B2
公开(公告)日：2008-09-30
申请号：US11080737
申请日：2005-03-15
申请人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
发明人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
IPC分类号： H01L21/764 , H01L31/0336
CPC分类号： H01L29/0653 , H01L29/78
摘要： Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.
摘要翻译：本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路，以及形成这种衬底和集成电路的方法。根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。在本发明的实施例中可以去除第二组IV图案。在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

2. 发明申请

US20080308845A1 Heterogeneous Group IV Semiconductor Substrates 审中-公开
标题翻译：异质IV族半导体基片
公开(公告)号：US20080308845A1
公开(公告)日：2008-12-18
申请号：US12195790
申请日：2008-08-21
申请人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
发明人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
IPC分类号： H01L29/00
CPC分类号： H01L29/0653 , H01L29/78
摘要： Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.
摘要翻译：本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路。根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。在本发明的实施例中可以去除第二组IV图案。在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

3. 发明申请

US20050218395A1 Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods 有权
标题翻译：异质IV族半导体衬底，形成在这种衬底上的集成电路及相关方法
公开(公告)号：US20050218395A1
公开(公告)日：2005-10-06
申请号：US11080737
申请日：2005-03-15
申请人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
发明人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
IPC分类号： H01L21/20 , H01L29/06 , H01L29/78
CPC分类号： H01L29/0653 , H01L29/78
摘要： Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.
摘要翻译：本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路，以及形成这种衬底和集成电路的方法。根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。在本发明的实施例中可以去除第二组IV图案。在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

4. 发明申请

US20100314604A1 Gate-all-around type semiconductor device and method of manufacturing the same 有权
标题翻译：栅极全周型半导体器件及其制造方法
公开(公告)号：US20100314604A1
公开(公告)日：2010-12-16
申请号：US12805776
申请日：2010-08-19
申请人： Sung-Dae Suk , Dong-Won Kim , Kyoung-Hwan Yeo
发明人： Sung-Dae Suk , Dong-Won Kim , Kyoung-Hwan Yeo
IPC分类号： H01L29/775
CPC分类号： H01L29/78696 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/42392
摘要： The gate-all-around (GAA) type semiconductor device may include source/drain layers, a nanowire channel, a gate electrode and an insulation layer pattern. The source/drain layers may be disposed at a distance in a first direction on a semiconductor substrate. The nanowire channel may connect the source/drain layers. The gate electrode may extend in a second direction substantially perpendicular to the first direction. The gate electrode may have a height in a third direction substantially perpendicular to the first and second directions and may partially surround the nanowire channel. The insulation layer pattern may be formed between and around the source/drain layers on the semiconductor substrate and may cover the nanowire channel and a portion of the gate electrode. Thus, a size of the gate electrode may be reduced, and/or a gate induced drain leakage (GIDL) and/or a gate leakage current may be reduced.
摘要翻译：栅极全能（GAA）型半导体器件可以包括源极/漏极层，纳米线沟道，栅电极和绝缘层图案。源极/漏极层可以在半导体衬底上沿第一方向设置一定距离。纳米线通道可以连接源极/漏极层。栅电极可以在基本上垂直于第一方向的第二方向上延伸。栅电极可以具有基本上垂直于第一和第二方向的第三方向的高度，并且可以部分地包围纳米线通道。绝缘层图案可以形成在半导体衬底上的源极/漏极层之间和周围，并且可以覆盖纳米线沟道和栅电极的一部分。因此，可以减小栅电极的尺寸，和/或栅极感应漏极泄漏（GIDL）和/或栅极泄漏电流可能降低。

5. 发明授权

US07803675B2 Gate-all-around type semiconductor device and method of manufacturing the same 有权
公开(公告)号：US07803675B2
公开(公告)日：2010-09-28
申请号：US11905511
申请日：2007-10-02
申请人： Sung-Dae Suk , Dong-Won Kim , Kyoung-Hwan Yeo
发明人： Sung-Dae Suk , Dong-Won Kim , Kyoung-Hwan Yeo
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/42392
摘要： The gate-all-around (GAA) type semiconductor device may include source/drain layers, a nanowire channel, a gate electrode and an insulation layer pattern. The source/drain layers may be disposed at a distance in a first direction on a semiconductor substrate. The nanowire channel may connect the source/drain layers. The gate electrode may extend in a second direction substantially perpendicular to the first direction. The gate electrode may have a height in a third direction substantially perpendicular to the first and second directions and may partially surround the nanowire channel. The insulation layer pattern may be formed between and around the source/drain layers on the semiconductor substrate and may cover the nanowire channel and a portion of the gate electrode. Thus, a size of the gate electrode may be reduced, and/or a gate induced drain leakage (GIDL) and/or a gate leakage current may be reduced.

6. 发明申请

US20100035398A1 Field effect transistor and method for manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20100035398A1
公开(公告)日：2010-02-11
申请号：US12588193
申请日：2009-10-07
申请人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Dong-Uk Choi , Kyoung-Hwan Yeo
发明人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Dong-Uk Choi , Kyoung-Hwan Yeo
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/1054 , H01L29/665 , H01L29/66621 , H01L29/66636 , H01L29/66651 , H01L29/66795 , H01L29/7851 , H01L29/78687 , H01L29/7881
摘要： A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.
摘要翻译：场效应晶体管（FET）及其制造方法，其中FET可以包括形成在半导体衬底上以形成有源区的隔离膜，以及形成在半导体衬底的给定部分上的栅电极。沟道层可以形成在栅电极的一部分上，源极和漏极区形成在沟道层的任一侧上，使得沟道层与FET的源极和漏极区之间的边界可以垂直于半导体衬底。

7. 发明申请

US20120058613A1 FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20120058613A1
公开(公告)日：2012-03-08
申请号：US13284889
申请日：2011-10-29
申请人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Dong-Uk Choi , Kyoung-Hwan Yeo
发明人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Dong-Uk Choi , Kyoung-Hwan Yeo
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/1054 , H01L29/665 , H01L29/66621 , H01L29/66636 , H01L29/66651 , H01L29/66795 , H01L29/7851 , H01L29/78687 , H01L29/7881
摘要： A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.
摘要翻译：场效应晶体管（FET）及其制造方法，其中FET可以包括形成在半导体衬底上以形成有源区的隔离膜，以及形成在半导体衬底的给定部分上的栅电极。沟道层可以形成在栅电极的一部分上，源极和漏极区形成在沟道层的任一侧上，使得沟道层与FET的源极和漏极区之间的边界可以垂直于半导体衬底。

8. 发明授权

US07361545B2 Field effect transistor with buried gate pattern 有权
标题翻译：具有掩埋栅极图案的场效应晶体管
公开(公告)号：US07361545B2
公开(公告)日：2008-04-22
申请号：US11241611
申请日：2005-09-30
申请人： Ming Li , Dong-Uk Choi , Chang-Woo Oh , Dong-Won Kim , Min-Sang Kim , Sung-Hwan Kim , Kyoung-Hwan Yeo
发明人： Ming Li , Dong-Uk Choi , Chang-Woo Oh , Dong-Won Kim , Min-Sang Kim , Sung-Hwan Kim , Kyoung-Hwan Yeo
IPC分类号： H01L21/00
CPC分类号： H01L29/7883 , H01L27/108 , H01L27/10802 , H01L29/42336 , H01L29/42392 , H01L29/66825 , H01L29/7841
摘要： A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.
摘要翻译：场效应晶体管包括通过被隧道绝缘膜包围而电隔离的掩埋栅极图案。场效应晶体管还包括由源极和漏极区域浮置的沟道区，栅极绝缘膜和隧道绝缘膜。掩埋栅极图案和隧道绝缘膜延伸到源极和漏极区域。因此，场效应晶体管有效地将电荷载流子存储在掩埋栅极图案和浮动沟道区域中。

9. 发明申请

US20080079041A1 Gate-all-around type semiconductor device and method of manufacturing the same 有权
标题翻译：栅极全周型半导体器件及其制造方法
公开(公告)号：US20080079041A1
公开(公告)日：2008-04-03
申请号：US11905511
申请日：2007-10-02
申请人： Sung-Dae Suk , Dong-Won Kim , Kyoung-Hwan Yeo
发明人： Sung-Dae Suk , Dong-Won Kim , Kyoung-Hwan Yeo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78696 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/42392
摘要： The gate-all-around (GAA) type semiconductor device may include source/drain layers, a nanowire channel, a gate electrode and an insulation layer pattern. The source/drain layers may be disposed at a distance in a first direction on a semiconductor substrate. The nanowire channel may connect the source/drain layers. The gate electrode may extend in a second direction substantially perpendicular to the first direction. The gate electrode may have a height in a third direction substantially perpendicular to the first and second directions and may partially surround the nanowire channel. The insulation layer pattern may be formed between and around the source/drain layers on the semiconductor substrate and may cover the nanowire channel and a portion of the gate electrode. Thus, a size of the gate electrode may be reduced, and/or a gate induced drain leakage (GIDL) and/or a gate leakage current may be reduced.
摘要翻译：栅极全能（GAA）型半导体器件可以包括源极/漏极层，纳米线沟道，栅电极和绝缘层图案。源极/漏极层可以在半导体衬底上沿第一方向设置一定距离。纳米线通道可以连接源极/漏极层。栅电极可以在基本上垂直于第一方向的第二方向上延伸。栅电极可以具有基本上垂直于第一和第二方向的第三方向的高度，并且可以部分地包围纳米线通道。绝缘层图案可以形成在半导体衬底上的源极/漏极层之间和周围，并且可以覆盖纳米线沟道和栅电极的一部分。因此，可以减小栅电极的尺寸，和/或栅极感应漏极泄漏（GIDL）和/或栅极泄漏电流可能降低。

10. 发明授权

US08101475B2 Field effect transistor and method for manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US08101475B2
公开(公告)日：2012-01-24
申请号：US12588193
申请日：2009-10-07
申请人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Dong-Uk Choi , Kyoung-Hwan Yeo
发明人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Dong-Uk Choi , Kyoung-Hwan Yeo
IPC分类号： H01L21/00
CPC分类号： H01L29/0847 , H01L29/1054 , H01L29/665 , H01L29/66621 , H01L29/66636 , H01L29/66651 , H01L29/66795 , H01L29/7851 , H01L29/78687 , H01L29/7881
摘要： A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.
摘要翻译：场效应晶体管（FET）及其制造方法，其中FET可以包括形成在半导体衬底上以形成有源区的隔离膜，以及形成在半导体衬底的给定部分上的栅电极。沟道层可以形成在栅电极的一部分上，源极和漏极区形成在沟道层的任一侧上，使得沟道层与FET的源极和漏极区之间的边界可以垂直于半导体衬底。

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