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1. 发明申请

US20090142892A1 Method of fabricating semiconductor device having thin strained relaxation buffer pattern and related device 审中-公开
标题翻译：制造具有薄应变松弛缓冲图案的半导体器件及其相关器件的方法
公开(公告)号：US20090142892A1
公开(公告)日：2009-06-04
申请号：US11984538
申请日：2007-11-19
申请人： Byeong-Chan Lee , Si-Young Choi , Yong-Hoon Son , In-Soo Jung , Min-Gu Kang , Pil-Kyu Kang
发明人： Byeong-Chan Lee , Si-Young Choi , Yong-Hoon Son , In-Soo Jung , Min-Gu Kang , Pil-Kyu Kang
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L21/823807 , H01L21/28052 , H01L21/823892 , H01L29/1054 , H01L29/4933 , H01L29/517
摘要： A method of fabricating a semiconductor device includes forming a buffer pattern on a substrate, the buffer pattern including germanium, recrystallizing the buffer pattern to form a strained relaxation buffer pattern, and forming a tensile silicon cap on the strained relaxation buffer pattern, the cap being under tensile strain.
摘要翻译：制造半导体器件的方法包括在衬底上形成缓冲图案，缓冲图案包括锗，使缓冲图案重结晶，形成应变弛豫缓冲图案，并在应变张弛缓冲图案上形成拉伸硅帽，在拉伸应变下。

2. 发明申请

US20080093601A1 Integrated circuit devices including a transcription-preventing pattern and methods of manufacturing the same 失效
标题翻译：包括转录阻止图案的集成电路装置及其制造方法
公开(公告)号：US20080093601A1
公开(公告)日：2008-04-24
申请号：US11974293
申请日：2007-10-12
申请人： Pil-Kyu Kang , Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Byeong-Chan Lee , In-Soo Jung
发明人： Pil-Kyu Kang , Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Byeong-Chan Lee , In-Soo Jung
IPC分类号： H01L29/786 , H01L29/12 , H01L21/84
CPC分类号： H01L21/823425 , H01L21/823475
摘要： Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating layer pattern and the seed layer. The second single-crystalline layer has a crystalline structure substantially the same as that of the seed layer. A transcription-preventing pattern is on the second single-crystalline layer and a third single-crystalline layer on the transcription-preventing pattern and the second single-crystalline layer. The transcription-preventing pattern is configured to limit transcription of defective portions in the second single-crystalline layer into the third single-crystalline layer.
摘要翻译：在第一单晶层上提供包括第一单晶层和绝缘层图案的集成电路器件。绝缘层图案在其中具有部分地暴露第一单晶层的开口。种子层在开口处。第二单晶层位于绝缘层图案和籽晶层上。第二单晶层具有与种子层基本相同的晶体结构。转录阻止图案位于转录阻止图案和第二单晶层上的第二单晶层和第三单晶层上。转录阻止图案被配置为将第二单晶层中的缺陷部分的转录限制为第三单晶层。

3. 发明授权

US07816735B2 Integrated circuit devices including a transcription-preventing pattern 失效
标题翻译：集成电路装置，包括转录阻止图案
公开(公告)号：US07816735B2
公开(公告)日：2010-10-19
申请号：US11974293
申请日：2007-10-12
申请人： Pil-Kyu Kang , Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Byeong-Chan Lee , InSoo Jung
发明人： Pil-Kyu Kang , Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Byeong-Chan Lee , InSoo Jung
IPC分类号： H01L33/16
CPC分类号： H01L21/823425 , H01L21/823475
摘要： Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating layer pattern and the seed layer. The second single-crystalline layer has a crystalline structure substantially the same as that of the seed layer. A transcription-preventing pattern is on the second single-crystalline layer and a third single-crystalline layer on the transcription-preventing pattern and the second single-crystalline layer. The transcription-preventing pattern is configured to limit transcription of defective portions in the second single-crystalline layer into the third single-crystalline layer.
摘要翻译：在第一单晶层上提供包括第一单晶层和绝缘层图案的集成电路器件。绝缘层图案在其中具有部分地暴露第一单晶层的开口。种子层在开口处。第二单晶层位于绝缘层图案和籽晶层上。第二单晶层具有与种子层基本相同的晶体结构。转录阻止图案位于转录阻止图案和第二单晶层上的第二单晶层和第三单晶层上。转录阻止图案被配置为将第二单晶层中的缺陷部分的转录限制为第三单晶层。

4. 发明申请

US20100330753A1 METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES INCLUDING A TRANSCRIPTION-PREVENTING PATTERN 审中-公开
标题翻译：制造包含转录预防图案的集成电路设备的方法
公开(公告)号：US20100330753A1
公开(公告)日：2010-12-30
申请号：US12879401
申请日：2010-09-10
申请人： Pil-Kyu Kang , Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Byeong-Chan Lee , InSoo Jung
发明人： Pil-Kyu Kang , Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Byeong-Chan Lee , InSoo Jung
IPC分类号： H01L21/336 , C30B1/02
CPC分类号： H01L21/823425 , H01L21/823475
摘要： Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating layer pattern and the seed layer. The second single-crystalline layer has a crystalline structure substantially the same as that of the seed layer. A transcription-preventing pattern is on the second single-crystalline layer and a third single-crystalline layer on the transcription-preventing pattern and the second single-crystalline layer. The transcription-preventing pattern is configured to limit transcription of defective portions in the second single-crystalline layer into the third single-crystalline layer.
摘要翻译：在第一单晶层上提供包括第一单晶层和绝缘层图案的集成电路器件。绝缘层图案在其中具有部分地暴露第一单晶层的开口。种子层在开口处。第二单晶层位于绝缘层图案和籽晶层上。第二单晶层具有与种子层基本相同的晶体结构。转录阻止图案位于转录阻止图案和第二单晶层上的第二单晶层和第三单晶层上。转录阻止图案被配置为将第二单晶层中的缺陷部分的转录限制为第三单晶层。

5. 发明申请

US20120034746A1 Methods of Fabricating MOS Transistors Having Recesses With Elevated Source/Drain Regions 有权
标题翻译：制造具有高的源极/漏极区域的凹槽的MOS晶体管的方法
公开(公告)号：US20120034746A1
公开(公告)日：2012-02-09
申请号：US13241311
申请日：2011-09-23
申请人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Deok-Hyung Lee , In-Soo Jung
发明人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Deok-Hyung Lee , In-Soo Jung
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/66636 , H01L29/7833
摘要： Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.
摘要翻译：提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管的制造方法。通过这些方法形成的MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。凹陷区域设置在与栅极图案相邻的衬底中。外凹层设置在凹陷区域的底表面上。在外延层中设置高浓度杂质区。凹陷区域可以使用化学干蚀刻技术形成。

6. 发明申请

US20100041201A1 Methods of Fabricating MOS Transistors Having Recesses with Elevated Source/Drain Regions 有权
标题翻译：制造具有高的源极/漏极区域的凹陷的MOS晶体管的方法
公开(公告)号：US20100041201A1
公开(公告)日：2010-02-18
申请号：US12582073
申请日：2009-10-20
申请人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Deok-Hyung Lee , In-Soo Jung
发明人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Deok-Hyung Lee , In-Soo Jung
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/66636 , H01L29/7833
摘要： Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.
摘要翻译：提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管的制造方法。通过这些方法形成的MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。凹陷区域设置在与栅极图案相邻的衬底中。外凹层设置在凹陷区域的底表面上。在外延层中设置高浓度杂质区。凹陷区域可以使用化学干蚀刻技术形成。

7. 发明授权

US07642589B2 Fin field effect transistors having capping insulation layers 有权
标题翻译： Fin场效应晶体管具有封盖绝缘层
公开(公告)号：US07642589B2
公开(公告)日：2010-01-05
申请号：US11433942
申请日：2006-05-15
申请人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Deok-Hyung Lee , In-Soo Jung
发明人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Deok-Hyung Lee , In-Soo Jung
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94
CPC分类号： H01L29/7851 , H01L21/823431 , H01L27/12 , H01L29/66795
摘要： A field effect transistor includes a vertical fin-shaped semiconductor active region having an upper surface and a pair of opposing sidewalls on a substrate, and an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region. The insulated gate electrode includes a capping gate insulation layer having a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface of the fin-shaped active region when the transistor is disposed in a forward on-state mode of operation. Related fabrication methods are also discussed.
摘要翻译：场效应晶体管包括在衬底上具有上表面和一对相对侧壁的垂直鳍状半导体有源区，以及鳍状有源区的上表面和相对侧壁上的绝缘栅电极。绝缘栅电极包括封盖栅极绝缘层，当晶体管处于正向导通状态工作模式时，其具有足以防止在鳍状有源区的上表面形成反型层通道的厚度。还讨论了相关的制造方法。

8. 发明授权

US07521301B2 Methods for fabricating integrated circuit field effect transistors including channel-containing fin having regions of high and low doping concentrations 有权
标题翻译：制造集成电路场效应晶体管的方法，其包括具有高掺杂浓度和低掺杂浓度区域的含通道翅片
公开(公告)号：US07521301B2
公开(公告)日：2009-04-21
申请号：US11530651
申请日：2006-09-11
申请人： Deok-Hyung Lee , Byeong-Chan Lee , Si-Young Choi , Taek-Jung Kim , Yong-Hoon Son , In-Soo Jung
发明人： Deok-Hyung Lee , Byeong-Chan Lee , Si-Young Choi , Taek-Jung Kim , Yong-Hoon Son , In-Soo Jung
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L21/823412 , H01L21/823437 , H01L29/66803
摘要： Integrated circuit field effect transistors include an integrated circuit substrate and a fin that projects away from the integrated circuit substrate, extends along the integrated circuit substrate, and includes a top that is remote from the integrated circuit substrate. A channel region is provided in the fin that is doped a conductivity type and has a higher doping concentration of the conductivity type adjacent the top than remote from the top. A source region and a drain region are provided in the fin on opposite sides of the channel region, and an insulated gate electrode extends across the fin adjacent the channel region. Related fabrication methods also are described.
摘要翻译：集成电路场效应晶体管包括集成电路基板和远离集成电路基板突出的翅片，沿着集成电路基板延伸，并且包括远离集成电路基板的顶部。沟道区域设置在散热片中，其掺杂有导电类型，并且具有比远离顶部更靠近顶部的导电类型的较高的掺杂浓度。源极区域和漏极区域设置在沟道区域的相对侧上的鳍片中，并且绝缘栅极电极在与沟道区域相邻的鳍片上延伸。还描述了相关的制造方法。

9. 发明申请

US20080308845A1 Heterogeneous Group IV Semiconductor Substrates 审中-公开
标题翻译：异质IV族半导体基片
公开(公告)号：US20080308845A1
公开(公告)日：2008-12-18
申请号：US12195790
申请日：2008-08-21
申请人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
发明人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
IPC分类号： H01L29/00
CPC分类号： H01L29/0653 , H01L29/78
摘要： Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.
摘要翻译：本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路。根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。在本发明的实施例中可以去除第二组IV图案。在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

10. 发明授权

US07320908B2 Methods of forming semiconductor devices having buried oxide patterns 有权
标题翻译：形成具有掩埋氧化物图案的半导体器件的方法
公开(公告)号：US07320908B2
公开(公告)日：2008-01-22
申请号：US11072103
申请日：2005-03-04
申请人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Jong-Wook Lee , In-Soo Jung , Deok-Hyung Lee
发明人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Jong-Wook Lee , In-Soo Jung , Deok-Hyung Lee
IPC分类号： H01L21/338
CPC分类号： H01L29/7851 , H01L21/823481 , H01L29/0653 , H01L29/66545 , H01L29/66621
摘要： Methods for forming semiconductor devices are provided. A semiconductor substrate is etched such that the semiconductor substrate defines a trench and a preliminary active pattern. The trench has a floor and a sidewall. An insulating layer is provided on the floor and the sidewall of the trench and a spacer is formed on the insulating layer such that the spacer is on the sidewall of the trench and on a portion of the floor of the trench. The insulating layer is removed on the floor of the trench and beneath the spacer such that a portion of the floor of the trench is at least partially exposed, the spacer is spaced apart from the floor of the trench and a portion of the preliminary active pattern is partially exposed. A portion of the exposed portion of the preliminary active pattern is partially removed to provide an active pattern that defines a recessed portion beneath the spacer. A buried insulating layer is formed in the recessed portion of the active pattern. Related devices are also provided.
摘要翻译：提供了形成半导体器件的方法。蚀刻半导体衬底，使得半导体衬底限定沟槽和初步活性图案。沟槽具有地板和侧壁。绝缘层设置在地板上，并且沟槽的侧壁和间隔件形成在绝缘层上，使得间隔件位于沟槽的侧壁和沟槽底部的一部分上。绝缘层在沟槽的地板上移除并且在间隔物的下面被移除，使得沟槽的底部的一部分至少部分地露出，间隔物与沟槽的底部间隔开，并且预活性图案的一部分部分暴露。部分地去除预活性图案的暴露部分的一部分以提供在间隔物下方限定凹陷部分的活性图案。在活性图案的凹部中形成掩埋绝缘层。还提供了相关设备。

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