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1. 发明授权

US08273620B2 Semiconductor integrated circuit device and related fabrication method 有权
标题翻译：半导体集成电路器件及相关制造方法
公开(公告)号：US08273620B2
公开(公告)日：2012-09-25
申请号：US12793809
申请日：2010-06-04
申请人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
发明人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
IPC分类号： H01L21/8234
CPC分类号： H01L21/823418 , H01L21/823456 , H01L27/105 , H01L27/1052
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由隔离区。半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

2. 发明授权

US07755133B2 Semiconductor integrated circuit device and related fabrication method 有权
标题翻译：半导体集成电路器件及相关制造方法
公开(公告)号：US07755133B2
公开(公告)日：2010-07-13
申请号：US11855529
申请日：2007-09-14
申请人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
发明人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
IPC分类号： H01L29/788
CPC分类号： H01L21/823418 , H01L21/823456 , H01L27/105 , H01L27/1052
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由隔离区。半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

3. 发明申请

US20060292783A1 CMOS transistor and method of manufacturing the same 有权
标题翻译： CMOS晶体管及其制造方法
公开(公告)号：US20060292783A1
公开(公告)日：2006-12-28
申请号：US11363176
申请日：2006-02-28
申请人： Young-eun Lee , Seong-ghil Lee , Yu-gyun Shin , Jong-wook Lee , Young-pil Kim
发明人： Young-eun Lee , Seong-ghil Lee , Yu-gyun Shin , Jong-wook Lee , Young-pil Kim
IPC分类号： H01L21/8238 , H01L29/80
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conductivity type MOS transistor also comprises a source/drain region formed in relation to an epitaxial layer formed in a recess region.
摘要翻译：公开了一种CMOS晶体管结构及相关的制造方法，其中第一导电型MOS晶体管包括增强器，第二导电类型MOS晶体管包括由与增强器相同的材料形成的第二间隔物。第二导电型MOS晶体管还包括相对于形成在凹陷区域中的外延层形成的源极/漏极区域。

4. 发明授权

US07315063B2 CMOS transistor and method of manufacturing the same 有权
标题翻译： CMOS晶体管及其制造方法
公开(公告)号：US07315063B2
公开(公告)日：2008-01-01
申请号：US11363176
申请日：2006-02-28
申请人： Young-eun Lee , Seong-ghil Lee , Yu-gyun Shin , Jong-wook Lee , Young-pil Kim
发明人： Young-eun Lee , Seong-ghil Lee , Yu-gyun Shin , Jong-wook Lee , Young-pil Kim
IPC分类号： H01L29/76
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conductivity type MOS transistor also comprises a source/drain region formed in relation to an epitaxial layer formed in a recess region.
摘要翻译：公开了一种CMOS晶体管结构及相关的制造方法，其中第一导电型MOS晶体管包括增强器，第二导电类型MOS晶体管包括由与增强器相同的材料形成的第二间隔物。第二导电型MOS晶体管还包括相对于形成在凹陷区域中的外延层形成的源极/漏极区域。

5. 发明授权

US08218360B2 Phase-change and resistance-change random access memory devices and related methods of performing burst mode operations in such memory devices 有权
标题翻译：相变和电阻变化随机存取存储器件以及在这种存储器件中执行突发模式操作的相关方法
公开(公告)号：US08218360B2
公开(公告)日：2012-07-10
申请号：US12582880
申请日：2009-10-21
申请人： Kwang-Jin Lee , Young-kug Moon , Young-pil Kim
发明人： Kwang-Jin Lee , Young-kug Moon , Young-pil Kim
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/004 , G11C7/1018 , G11C8/18 , G11C11/5678 , G11C13/00 , G11C13/0004
摘要： Phase-change and resistance-change random access memory devices are provided which include a phase-change or resistance-change memory cell array and a sense amplifier that is configured to amplify data read from the phase-change memory cell array. These random access memory devices are configured to read data from a first word line of the phase-change or resistance-change memory cell array and to insert a dummy burst in which no data is read when a first boundary crossing occurs during a burst mode operation. Related methods of operating phase-change and/or resistance-change random access memory devices in burst mode are also provided.
摘要翻译：提供了相变和电阻变化随机存取存储器件，其包括相变或电阻变化存储单元阵列和被配置为放大从相变存储单元阵列读取的数据的读出放大器。这些随机存取存储器件被配置为从相变或电阻变化存储单元阵列的第一字线读取数据，并且在突发模式操作期间发生第一边界交叉时插入其中没有读取数据的虚拟脉冲串。还提供了以突发模式操作相变和/或电阻变化随机存取存储器件的相关方法。

6. 发明申请

US20100124102A1 Phase-Change and Resistance-Change Random Access Memory Devices and Related Methods of Performing Burst Mode Operations in Such Memory Devices 有权
标题翻译：相变和电阻变化随机存取存储器件以及在这种存储器件中执行突发模式操作的相关方法
公开(公告)号：US20100124102A1
公开(公告)日：2010-05-20
申请号：US12582880
申请日：2009-10-21
申请人： Kwang-Jin Lee , Young-kug Moon , Young-pil Kim
发明人： Kwang-Jin Lee , Young-kug Moon , Young-pil Kim
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/004 , G11C7/1018 , G11C8/18 , G11C11/5678 , G11C13/00 , G11C13/0004
摘要： Phase-change and resistance-change random access memory devices are provided which include a phase-change or resistance-change memory cell array and a sense amplifier that is configured to amplify data read from the phase-change memory cell array. These random access memory devices are configured to read data from a first word line of the phase-change or resistance-change memory cell array and to insert a dummy burst in which no data is read when a first boundary crossing occurs during a burst mode operation. Related methods of operating phase-change and/or resistance-change random access memory devices in burst mode are also provided.
摘要翻译：提供了相变和电阻变化随机存取存储器件，其包括相变或电阻变化存储单元阵列和被配置为放大从相变存储单元阵列读取的数据的读出放大器。这些随机存取存储器件被配置为从相变或电阻变化存储单元阵列的第一字线读取数据，并且在突发模式操作期间发生第一边界交叉时插入其中没有读取数据的虚拟脉冲串。还提供了以突发模式操作相变和/或电阻变化随机存取存储器件的相关方法。

7. 发明授权

US07271408B2 Semiconductor device test patterns and related methods for precisely measuring leakage currents in semiconductor cell transistors 失效
标题翻译：用于精确测量半导体单元晶体管中的漏电流的半导体器件测试图案和相关方法
公开(公告)号：US07271408B2
公开(公告)日：2007-09-18
申请号：US10796672
申请日：2004-03-09
申请人： Young-pil Kim , Beom-jun Jin
发明人： Young-pil Kim , Beom-jun Jin
IPC分类号： H01L23/58
CPC分类号： H01L27/10882 , H01L22/32 , H01L27/108 , H01L27/10814 , H01L27/10894 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor device test patterns are provided that include a word line on a semiconductor substrate and an active region having a first impurity doped region and a second impurity doped region in at the semiconductor substrate. A first self-aligned contact pad is electrically connected to the first impurity doped region, and a first direct contact is electrically connected to the first self-aligned contact pad. A first bit line is electrically connected to the first direct contact, and a first probing pad is electrically connected to the first bit line. The test pattern further includes a second self-aligned contact pad that is electrically connected to the second impurity doped region, and a second direct contact electrically connected to the second self-aligned contact pad. A second conductive line is electrically connected to the second direct contact, and a second probing pad is electrically connected to the second conductive line. These test patterns may be used to measure leakage current in a cell transistor of the semiconductor device.
摘要翻译：提供半导体器件测试图案，其包括在半导体衬底上的字线和在半导体衬底中具有第一杂质掺杂区和第二杂质掺杂区的有源区。第一自对准接触焊盘电连接到第一杂质掺杂区域，第一直接接触电连接到第一自对准接触焊盘。第一位线电连接到第一直接触点，并且第一探针焊盘电连接到第一位线。测试图案还包括电连接到第二杂质掺杂区的第二自对准接触焊盘和电连接到第二自对准接触焊盘的第二直接接触。第二导电线电连接到第二直接接触，第二探测焊盘电连接到第二导线。这些测试图案可用于测量半导体器件的单元晶体管中的漏电流。

8. 发明授权

US07864619B2 Write driver circuit for phase-change memory, memory including the same, and associated methods 有权
标题翻译：为相变存储器写入驱动电路，包含相同的存储器及相关方法
公开(公告)号：US07864619B2
公开(公告)日：2011-01-04
申请号：US12292200
申请日：2008-11-13
申请人： Beak-hyung Cho , Kwang-ho Kim , Young-pil Kim
发明人： Beak-hyung Cho , Kwang-ho Kim , Young-pil Kim
IPC分类号： G11C8/00 , G11C5/14 , G11C11/00
CPC分类号： G11C13/0038 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/0069 , G11C2013/0078
摘要： A write driver circuit for a memory that includes phase-change memory cells changeable between a RESET state resistance and a SET state resistance in response to an applied current pulse, the write driver circuit including a write current level adjusting unit configured to determine first to n-th SET state current levels in response to a SET state current level signal, where n is an integer greater than 1, and configured to determine a RESET state current level in response to a RESET state current level signal, and a write current output unit configured to generate one of a SET state current pulse and a RESET state current pulse corresponding to a SET state current level or a RESET state current level determined by the write current level adjusting unit.
摘要翻译：一种用于存储器的写入驱动器电路，其包括响应于所施加的电流脉冲而在RESET状态电阻和SET状态电阻之间改变的相变存储器单元，所述写入驱动器电路包括写入电平电平调整单元，其被配置为从第一至第n 响应于SET状态电流电平信号，其中n是大于1的整数，并且被配置为响应于RESET状态电流信号确定RESET状态电流电平，并且写入电流输出单元被配置为产生与由写入电平电平调整单元确定的SET状态电流电平或RESET状态电流电平对应的SET状态电流脉冲和RESET状态电流脉冲之一。

9. 发明授权

US06689654B2 Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad 有权
标题翻译：制造在基板和接触垫之间具有降低的接触电阻同时保持基板和接触垫的分离的集成电路器件的方法
公开(公告)号：US06689654B2
公开(公告)日：2004-02-10
申请号：US10038967
申请日：2002-01-04
申请人： Young-pil Kim , Beom-jun Jin , Hyoung-joon Kim , Byeong-yun Nam
发明人： Young-pil Kim , Beom-jun Jin , Hyoung-joon Kim , Byeong-yun Nam
IPC分类号： H01L218238
CPC分类号： H01L21/76897 , H01L21/28525 , H01L21/76895 , H01L21/823425 , H01L21/823475
摘要： An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.
摘要翻译：集成电路器件包括其中形成有源极区和漏极区的衬底。在源极区域和漏极区域之间的衬底上设置栅极图案。下焊盘层设置在源极区域和/或漏极区域上并且包括与衬底相同的晶体结构。导电层设置在下焊盘层上，使得导电层的至少一部分设置在下焊盘层和栅极图案之间。绝缘层设置在栅极图案与下焊盘层和导电层之间以及导电层和基板之间。

10. 发明授权

US5981324A Methods of forming integrated circuits having memory cell arrays and peripheral circuits therein 失效
标题翻译：在其中形成具有存储单元阵列和外围电路的集成电路的方法
公开(公告)号：US5981324A
公开(公告)日：1999-11-09
申请号：US956584
申请日：1997-10-23
申请人： Young-woo Seo , Young-pil Kim , Myeon-koo Kang , Won-shik Lee
发明人： Young-woo Seo , Young-pil Kim , Myeon-koo Kang , Won-shik Lee
IPC分类号： H01L21/8239 , H01L21/8242
CPC分类号： H01L27/10844 , H01L27/1052
摘要： Methods of forming integrated circuits having memory cell arrays therein and peripheral circuits therein include the steps of selectively forming more lightly doped source and drain regions for transistors in the memory cell arrays. These more lightly doped source and drain regions are designed to have fewer crystalline defects therein caused by ion implantation, so that storage capacitors coupled thereto have improved refresh characteristics. Preferred methods include the steps of forming a first well region of first conductivity type (e.g., P-type) in a memory cell portion of a semiconductor substrate and a second well region of first conductivity type in a peripheral circuit portion of the semiconductor substrate extending adjacent the memory cell portion. First and second insulated gate electrodes are then formed on the first and second well regions, respectively, using conventional techniques. First dopants of second conductivity type are then implanted at a first dose level into the first and second well regions, using the first and second insulated gate electrodes as an implant mask. These dopants are then diffused to form lightly doped source and drain regions adjacent the first and second insulated gate electrodes. Second dopants of second conductivity type are then selectively implanted at a second dose level, greater than the first dose level, into the second well region using self-alignment techniques. However, these dopants are preferably not implanted into the first well region. These second dopants are then diffused into the second source/drain regions.
摘要翻译：形成其中具有存储单元阵列的集成电路及其外围电路的方法包括以下步骤：为存储单元阵列中的晶体管选择性地形成更多的轻掺杂源极和漏极区域。这些更轻掺杂的源极和漏极区域被设计为在离子注入中具有较少的晶体缺陷，使得与其耦合的存储电容器具有改善的刷新特性。优选的方法包括以下步骤：在半导体衬底的存储单元部分中形成第一导电类型的第一阱区域（例如，P型）和在半导体衬底延伸的外围电路部分中的第一导电类型的第二阱区域邻近存储单元部分。然后使用常规技术分别在第一和第二阱区上形成第一和第二绝缘栅电极。然后使用第一和第二绝缘栅电极作为植入掩模，将第一导电类型的第一掺杂剂以第一剂量水平注入第一阱区和第二阱区。然后这些掺杂剂被扩散以形成与第一和第二绝缘栅电极相邻的轻掺杂源极和漏极区。然后使用自对准技术将第二导电类型的第二掺杂剂以大于第一剂量水平的第二剂量水平选择性地植入第二阱区。然而，这些掺杂剂优选不被植入第一阱区。然后将这些第二掺杂剂扩散到第二源/漏区。

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