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1. 发明授权

US06442632B1 System resource arbitration mechanism for a host bridge 有权
标题翻译：主机桥系统资源仲裁机制
公开(公告)号：US06442632B1
公开(公告)日：2002-08-27
申请号：US09662365
申请日：2000-09-13
申请人： George Hayek , Brian Langendorf , Aniruddha Kundu , Gary Solomon , Peter D. MacWilliams , James M. Dodd
发明人： George Hayek , Brian Langendorf , Aniruddha Kundu , Gary Solomon , Peter D. MacWilliams , James M. Dodd
IPC分类号： G06F1300
CPC分类号： G06F13/4031
摘要： A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.
摘要翻译：公开了一种计算机系统，其具有主机桥，其经由主机总线以及经由外围总线从一组总线代理仲裁对来自CPU的系统资源的访问。向CPU和总线代理提供了一组单独的优先级，并且包括可编程定时器来调整主机和处理器总线之间的系统资源分配。

2. 发明授权

US06212589B1 System resource arbitration mechanism for a host bridge 失效
标题翻译：主机桥系统资源仲裁机制
公开(公告)号：US06212589B1
公开(公告)日：2001-04-03
申请号：US08924209
申请日：1997-09-05
申请人： George Hayek , Brian Langendorf , Aniruddha Kundu , Gary Solomon , Peter D. MacWilliams , James M. Dodd
发明人： George Hayek , Brian Langendorf , Aniruddha Kundu , Gary Solomon , Peter D. MacWilliams , James M. Dodd
IPC分类号： G06F1300
CPC分类号： G06F13/4031
摘要： A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.
摘要翻译：公开了一种计算机系统，其具有主机桥，其经由主机总线以及经由外围总线从一组总线代理仲裁对来自CPU的系统资源的访问。向CPU和总线代理提供了一组单独的优先级，并且包括可编程定时器来调整主机和处理器总线之间的系统资源分配。

3. 发明授权

US07774651B2 System and method to detect errors and predict potential failures 有权
标题翻译：检测错误并预测潜在故障的系统和方法
公开(公告)号：US07774651B2
公开(公告)日：2010-08-10
申请号：US11970029
申请日：2008-01-07
申请人： Udayan Mukherjee , Aniruddha Kundu
发明人： Udayan Mukherjee , Aniruddha Kundu
IPC分类号： G06F11/00
CPC分类号： G06F11/0775 , G06F11/0724 , G06F11/076 , G06F11/079 , G06F11/0793
摘要： A system is disclosed that includes a component, a fault table configured to receive fault information associated with the component, and a diagnosis processor configured to read the fault information from the fault table and initiate corrective action as a function of the fault information. A method for handling faults in the system is also disclosed.
摘要翻译：公开了一种系统，其包括：组件，被配置为接收与所述组件相关联的故障信息的故障表;以及诊断处理器，被配置为从所述故障表读取所述故障信息，并根据所述故障信息启动校正动作。还公开了一种用于处理系统中的故障的方法。

4. 发明授权

US06112284A Method and apparatus for latching data from a memory resource at a datapath unit 失效
标题翻译：用于在数据路径单元处从存储器资源锁存数据的方法和装置
公开(公告)号：US06112284A
公开(公告)日：2000-08-29
申请号：US367807
申请日：1994-12-30
申请人： George R. Hayek , Joe M. Nardone , Aniruddha Kundu , Kuljit S. Bains
发明人： George R. Hayek , Joe M. Nardone , Aniruddha Kundu , Kuljit S. Bains
IPC分类号： G11C7/10 , G06F13/16
CPC分类号： G11C7/1018 , G11C7/1024
摘要： A memory controller having a data strobe that tracks the column access strobe signal in a computer system having Extended Data Out (EDO) DRAMs. The data strobe signal follows, by a predetermined delay, the column access strobe signal, and therefore any skew in the column access strobe signal is inherently included within the data strobe signal. As a result, the data can be latched out, responsive to said data strobe signal, at approximately the center of the valid window.
摘要翻译：具有在具有扩展数据输出（EDO）DRAM的计算机系统中跟踪列存取选通信号的数据选通器的存储器控制器。数据选通信号以预定的延迟跟随列存取选通信号，因此列存取选通信号中的任何偏移固有地包括在数据选通信号内。结果，可以在有效窗口的大约中心处响应于所述数据选通信号来锁存数据。

5. 发明授权

US5819096A PCI to ISA interrupt protocol converter and selection mechanism 失效
标题翻译： PCI到ISA中断协议转换器和选择机制
公开(公告)号：US5819096A
公开(公告)日：1998-10-06
申请号：US893447
申请日：1997-07-11
申请人： Albert R. Nelson , Aniruddha Kundu
发明人： Albert R. Nelson , Aniruddha Kundu
IPC分类号： G06F9/46 , G06F9/48 , G06F13/24
CPC分类号： G06F13/24
摘要： An interrupt handling mechanism for converting PCI agent interrupts into interrupts compliant with a secondary bus standard interrupt protocol. PCI agent interrupts are processed by programmable logic for converting PCI compliant interrupts into, for example, ISA bus standard compliant interrupts for processing by a computer system which implements both a PCI bus and ISA bus. A programmable register provides for selecting which ISA interrupt will be generated by the programmable logic in response to a PCI agent interrupt.
摘要翻译：一种用于将PCI代理中断转换为符合辅助总线标准中断协议的中断的中断处理机制。 PCI代理中断由可编程逻辑处理，用于将PCI兼容的中断转换为例如ISA总线标准兼容中断，以便由实现PCI总线和ISA总线的计算机系统进行处理。可编程寄存器用于选择可编程逻辑响应PCI代理中断产生的ISA中断。

6. 发明授权

US07453870B2 Backplane for switch fabric 有权
标题翻译：交换结构背板
公开(公告)号：US07453870B2
公开(公告)日：2008-11-18
申请号：US10171447
申请日：2002-06-12
申请人： Kuriappan P. Alappat , Brian Peebles , Aniruddha Kundu , Gerald Lebizay
发明人： Kuriappan P. Alappat , Brian Peebles , Aniruddha Kundu , Gerald Lebizay
IPC分类号： H04L12/50 , H04Q11/00
CPC分类号： H04L49/40 , H04L49/10 , H04L49/405
摘要： A backplane employed in a switch fabric, having the capability to allow signal communication between at least two modules. Two or more of the modules being adapted to employ different topologies from the following types of topologies: star, dual star, mesh, and cascaded mesh.
摘要翻译：在交换结构中采用的背板，具有允许至少两个模块之间的信号通信的能力。两个或更多个模块适于采用与以下类型拓扑结构不同的拓扑：星形，双星型，网状和级联网格。

7. 发明申请

US20060010352A1 System and method to detect errors and predict potential failures 有权
标题翻译：检测错误并预测潜在故障的系统和方法
公开(公告)号：US20060010352A1
公开(公告)日：2006-01-12
申请号：US10887368
申请日：2004-07-06
申请人： Udayan Mukherjee , Aniruddha Kundu
发明人： Udayan Mukherjee , Aniruddha Kundu
IPC分类号： G06F11/00
CPC分类号： G06F11/0775 , G06F11/0724 , G06F11/076 , G06F11/079 , G06F11/0793
摘要： A system is disclosed that includes a component, a fault table configured to receive fault information associated with the component, and a diagnosis processor configured to read the fault information from the fault table and initiate corrective action as a function of the fault information. A method for handling faults in the system is also disclosed.
摘要翻译：公开了一种系统，其包括：组件，被配置为接收与所述组件相关联的故障信息的故障表;以及诊断处理器，被配置为从所述故障表读取所述故障信息，并根据所述故障信息启动校正动作。还公开了一种用于处理系统中的故障的方法。

8. 发明授权

US06567904B1 Method and apparatus for automatically detecting whether a memory unit location is unpopulated or populated with synchronous or asynchronous memory devices 失效
标题翻译：用于自动检测存储器单元位置是未被填充还是用同步或异步存储器件填充的方法和装置
公开(公告)号：US06567904B1
公开(公告)日：2003-05-20
申请号：US08581378
申请日：1995-12-29
申请人： Narendra Khandekar , Aniruddha Kundu
发明人： Narendra Khandekar , Aniruddha Kundu
IPC分类号： G06F1200
CPC分类号： G11C7/1072 , G11C7/1021 , G11C7/1024 , G11C7/20 , G11C11/4072 , G11C2207/2254
摘要： A memory controller apparatus and method for automatically detecting whether a particular memory unit location is unpopulated or populated with synchronous dynamic random access memories (DRAMs), or asynchronous fast page (FP) DRAMs or extended data out (EDO) DRAMs are disclosed. Logic in the memory controller detects a memory device type by writing a first data item to the memory device using at least a minimum common asynchronous memory write protocol meeting the write timing requirements of all asynchronous memory device types. An attempt is then made to read the first data from the memory device using a first asynchronous memory read protocol. If the first data is read from the memory device, the memory device is identified as being an asynchronous memory. If the first data is not read from the device, the memory control logic writes a second data item to the memory device using a synchronous memory write protocol. An attempt is then made to read the second data from the memory device using a synchronous memory read protocol. If the second data is read, the memory device is identified as being a synchronous memory device. If the second data is not read, the memory unit is unpopulated. For one embodiment, the memory device type of each bank in a memory array is automatically stored in a configuration register such that a computer system is automatically configured to indicate memory device type.
摘要翻译：公开了一种用于通过同步动态随机存取存储器（DRAM）或异步快速页（FP）DRAM或扩展数据输出（EDO）DRAM来自动检测特定存储器单元位置是否未填充或填充的存储器控制器装置和方法。存储器控制器中的逻辑通过使用满足所有异步存储器设备类型的写定时要求的至少最小公共异步存储器写协议来将第一数据项写入存储器件来检测存储器件类型。然后尝试使用第一异步存储器读协议从存储器件读取第一数据。如果从存储器件读取第一数据，则存储器件被识别为异步存储器。如果第一数据未从设备读取，则存储器控制逻辑使用同步存储器写协议将第二数据项写入存储器件。然后尝试使用同步存储器读取协议从存储器件读取第二数据。如果读取第二数据，则将存储器件识别为同步存储器件。如果未读取第二数据，则存储器单元未被填充。对于一个实施例，存储器阵列中的每个存储体的存储器件类型被自动存储在配置寄存器中，使得计算机系统被自动配置为指示存储器件类型。

9. 发明授权

US5463744A Emulation of slower speed processor 失效
标题翻译：低速处理器的仿真
公开(公告)号：US5463744A
公开(公告)日：1995-10-31
申请号：US205352
申请日：1994-03-02
申请人： Aniruddha Kundu , Ali S. Oztaskin
发明人： Aniruddha Kundu , Ali S. Oztaskin
IPC分类号： G06F9/318 , G06F9/38 , G06F1/14
CPC分类号： G06F9/3869
摘要： A pulse width modulation circuit in a computer system for emulating a processor operating at a slower instruction execution speed. The pulse width modulator a computer system clock, and a register containing a first value. The first value is user-definable by software and specifies a proportion of time that a processor should remain idle. The apparatus further comprises a counter coupled to the clock, the counter having a range between a second and third values which includes the first value. A comparator is coupled to the counter and the register, and the comparator causes a central processing unit to suspend instruction execution for a specified interval of time. The comparator causes the central processing unit to resume instruction execution for remainder of the counter's range. The processor is therefore kept idle for proportions of time depending on the values of the register and the counter to emulate a slower speed processor. For high performance processors which have an on processor cache, the cache is flushed and disabled.
摘要翻译：一种用于模拟以较慢指令执行速度工作的处理器的计算机系统中的脉宽调制电路。脉冲宽度调制器计算机系统时钟，以及包含第一个值的寄存器。第一个值由软件用户定义，并指定处理器保持空闲的一段时间。该装置还包括耦合到时钟的计数器，该计数器具有包括第一值的第二和第三值之间的范围。比较器耦合到计数器和寄存器，并且比较器使得中央处理单元在指定的时间间隔内暂停指令执行。比较器使中央处理单元恢复指令执行计数器范围的剩余部分。因此，处理器根据寄存器和计数器的值保持空闲时间，以模拟较慢速度的处理器。对于具有处理器缓存的高性能处理器，缓存将被刷新并禁用。

10. 发明授权

US07409594B2 System and method to detect errors and predict potential failures 有权
标题翻译：检测错误并预测潜在故障的系统和方法
公开(公告)号：US07409594B2
公开(公告)日：2008-08-05
申请号：US10887368
申请日：2004-07-06
申请人： Udayan Mukherjee , Aniruddha Kundu
发明人： Udayan Mukherjee , Aniruddha Kundu
IPC分类号： G06F11/00
CPC分类号： G06F11/0775 , G06F11/0724 , G06F11/076 , G06F11/079 , G06F11/0793
摘要： A system is disclosed that includes a component, a fault table configured to receive fault information associated with the component, and a diagnosis processor configured to read the fault information from the fault table and initiate corrective action as a function of the fault information. A method for handling faults in the system is also disclosed.
摘要翻译：公开了一种系统，其包括：组件，被配置为接收与所述组件相关联的故障信息的故障表;以及诊断处理器，被配置为从所述故障表读取所述故障信息，并根据所述故障信息启动校正动作。还公开了一种用于处理系统中的故障的方法。

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