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1. 发明授权

US07363436B1 Collision detection in a multi-port memory system 有权
标题翻译：多端口存储系统中的碰撞检测
公开(公告)号：US07363436B1
公开(公告)日：2008-04-22
申请号：US10808253
申请日：2004-03-23
申请人： Tzong-Kwang Henry Yeh , Bill Beane , Chung Han Lin , Wei-Ling Chang
发明人： Tzong-Kwang Henry Yeh , Bill Beane , Chung Han Lin , Wei-Ling Chang
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G06F13/1605 , G11C8/16
摘要： A collision detection circuit for a multi-port memory system is presented. The collision detection circuit detects a collision condition if the addresses at two or more ports at the same time match and if one of the two or more ports is writing to the memory location associated with that address. A collision flag can then be set when the collision condition exists. In some embodiments, arbitration can occur when the collision flag is set.
摘要翻译：提出了一种用于多端口存储器系统的冲突检测电路。如果两个或多个端口上的地址同时匹配，并且两个或多个端口中的一个端口正在写入与该地址相关联的存储器位置，则冲突检测电路检测冲突条件。然后可以在碰撞条件存在时设置碰撞标志。在一些实施例中，当设置冲突标志时可能发生仲裁。

2. 发明申请

US20060277372A1 Systems and methods for monitoring and controlling binary state devices using a memory device 失效
标题翻译：使用存储设备监控和控制二进制状态设备的系统和方法
公开(公告)号：US20060277372A1
公开(公告)日：2006-12-07
申请号：US11503431
申请日：2006-08-10
申请人： Yunsheng Wang , Casey Springer , Tak Wong , Bill Beane
发明人： Yunsheng Wang , Casey Springer , Tak Wong , Bill Beane
IPC分类号： G06F13/28
CPC分类号： G11C7/1075 , G06F13/1663
摘要： A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device. Each bit of the ODR can manipulate the state of a connected external binary device or can be read without changing the state. The memory device may include settable controlling bits and a set of controlled register bits. Setting the one or more controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR.
摘要翻译：静态随机存取存储器（SRAM）包括用于监视外部二进制器件状态的输入读寄存器（IRR）和用于控制外部二进制器件状态的输出驱动寄存器（ODR）。 SRAM可以是多端口设备，用于多个处理器或控制器的访问。 IRR的每一位可以反映连接的外部二进制设备的状态。 ODR的每一位可以操纵连接的外部二进制设备的状态，或者可以在不改变状态的情况下读取。存储器件可以包括可设置的控制位和一组受控寄存器位。设置一个或多个控制位可以定义哪些受控寄存器位与IRR相关联并且与ODR相关联。

3. 发明授权

US07904667B2 Systems and methods for monitoring and controlling binary state devices using a memory device 失效
标题翻译：使用存储设备监控和控制二进制状态设备的系统和方法
公开(公告)号：US07904667B2
公开(公告)日：2011-03-08
申请号：US11503431
申请日：2006-08-10
申请人： Yunsheng Wang , Casey Springer , Tak Kwong Wong , Bill Beane
发明人： Yunsheng Wang , Casey Springer , Tak Kwong Wong , Bill Beane
IPC分类号： G06F13/20
CPC分类号： G11C7/1075 , G06F13/1663
摘要： A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device. Each bit of the ODR can manipulate the state of a connected external binary device or can be read without changing the state. The memory device may include settable controlling bits and a set of controlled register bits. Setting the one or more controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR.
摘要翻译：静态随机存取存储器（SRAM）包括用于监视外部二进制器件状态的输入读寄存器（IRR）和用于控制外部二进制器件状态的输出驱动寄存器（ODR）。 SRAM可以是多端口设备，用于多个处理器或控制器的访问。 IRR的每一位可以反映连接的外部二进制设备的状态。 ODR的每一位可以操纵连接的外部二进制设备的状态，或者可以在不改变状态的情况下读取。存储器件可以包括可设置的控制位和一组受控寄存器位。设置一个或多个控制位可以定义哪些受控寄存器位与IRR相关联并且与ODR相关联。

4. 发明授权

US07747828B2 Systems and methods for monitoring and controlling binary state devices using a memory device 有权
标题翻译：使用存储设备监控和控制二进制状态设备的系统和方法
公开(公告)号：US07747828B2
公开(公告)日：2010-06-29
申请号：US10992428
申请日：2004-11-17
申请人： Yunsheng Wang , Casey Springer , Tak Kwong Wong , Bill Beane
发明人： Yunsheng Wang , Casey Springer , Tak Kwong Wong , Bill Beane
IPC分类号： G06F13/20
CPC分类号： G11C7/1075 , G06F13/1663
摘要： A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.
摘要翻译：静态随机存取存储器（SRAM）包括用于监视外部二进制器件状态的输入读寄存器（IRR）和用于控制外部二进制器件状态的输出驱动寄存器（ODR）。 SRAM可以是多端口设备，用于多个处理器或控制器的访问。 IRR的每一位可以反映连接的外部二进制设备的状态，并可以使用标准读取指令读取到连接的处理器。 ODR的每一位可以通过为器件提供SRAM电源电压的路径来操纵连接的外部二进制器件的状态。也可以在不改变连接的外部二进制设备的状态或中断操作的情况下读取ODR的每个位。当设置为正确模式时，用于IRR和ODR的地址可以与SRAM主存储器阵列一起用于标准存储器操作。

5. 发明申请

US20060106989A1 Systems and methods for monitoring and controlling binary state devices using a memory device 有权
标题翻译：使用存储设备监控和控制二进制状态设备的系统和方法
公开(公告)号：US20060106989A1
公开(公告)日：2006-05-18
申请号：US10992428
申请日：2004-11-17
申请人： Yunsheng Wang , Casey Springer , Tak Wong , Bill Beane
发明人： Yunsheng Wang , Casey Springer , Tak Wong , Bill Beane
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G06F13/1663
摘要： A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.
摘要翻译：静态随机存取存储器（SRAM）包括用于监视外部二进制器件状态的输入读寄存器（IRR）和用于控制外部二进制器件状态的输出驱动寄存器（ODR）。 SRAM可以是多端口设备，用于多个处理器或控制器的访问。 IRR的每一位可以反映连接的外部二进制设备的状态，并可以使用标准读取指令读取到连接的处理器。 ODR的每一位可以通过为器件提供SRAM电源电压的路径来操纵连接的外部二进制器件的状态。也可以在不改变连接的外部二进制设备的状态或中断操作的情况下读取ODR的每个位。当设置为正确模式时，用于IRR和ODR的地址可以与SRAM主存储器阵列一起用于标准存储器操作。

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