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1. 发明授权

US07363436B1 Collision detection in a multi-port memory system 有权
标题翻译：多端口存储系统中的碰撞检测
公开(公告)号：US07363436B1
公开(公告)日：2008-04-22
申请号：US10808253
申请日：2004-03-23
申请人： Tzong-Kwang Henry Yeh , Bill Beane , Chung Han Lin , Wei-Ling Chang
发明人： Tzong-Kwang Henry Yeh , Bill Beane , Chung Han Lin , Wei-Ling Chang
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G06F13/1605 , G11C8/16
摘要： A collision detection circuit for a multi-port memory system is presented. The collision detection circuit detects a collision condition if the addresses at two or more ports at the same time match and if one of the two or more ports is writing to the memory location associated with that address. A collision flag can then be set when the collision condition exists. In some embodiments, arbitration can occur when the collision flag is set.
摘要翻译：提出了一种用于多端口存储器系统的冲突检测电路。如果两个或多个端口上的地址同时匹配，并且两个或多个端口中的一个端口正在写入与该地址相关联的存储器位置，则冲突检测电路检测冲突条件。然后可以在碰撞条件存在时设置碰撞标志。在一些实施例中，当设置冲突标志时可能发生仲裁。

2. 发明授权

US07443747B2 Memory array bit line coupling capacitor cancellation 有权
标题翻译：存储阵列位线耦合电容器取消
公开(公告)号：US07443747B2
公开(公告)日：2008-10-28
申请号：US10997708
申请日：2004-11-23
申请人： Chuen-Der Lien , Tzong-Kwang Henry Yeh
发明人： Chuen-Der Lien , Tzong-Kwang Henry Yeh
IPC分类号： G11C7/00
CPC分类号： G11C8/16 , G11C5/063 , G11C7/02 , G11C7/12 , G11C11/419
摘要： Capacitive coupling correction circuits are coupled between adjacent parallel dynamic (pre-charged) or static conductors. The capacitive coupling correction circuits effectively isolate a low voltage applied to a first conductor from a high pre-charged voltage stored on an adjacent second conductor (or vice versa). The adjacent parallel conductors can be bit lines of a memory cell. Each capacitive coupling correction circuit can include an inverter having an input terminal coupled to the first conductor, and an output terminal coupled to a first plate of a capacitor. A second plate of the capacitor is coupled to the second conductor. The capacitance of the capacitor is selected to be identical to a parasitic capacitance between the first and second conductors. As a result, there is a zero net voltage effect between the first and second conductors. The capacitive coupling correction circuits may be distributed along the length of the first and second conductors.
摘要翻译：电容耦合校正电路耦合在相邻的并联动态（预充电）或静态导体之间。电容耦合校正电路有效地将施加到第一导体的低电压与存储在相邻的第二导体上的高预充电电压隔离（反之亦然）。相邻的平行导体可以是存储单元的位线。每个电容耦合校正电路可以包括具有耦合到第一导体的输入端的反相器和耦合到电容器的第一板的输出端。电容器的第二板耦合到第二导体。电容器的电容被选择为与第一和第二导体之间的寄生电容相同。结果，在第一和第二导体之间存在零净电压效应。电容耦合校正电路可以沿着第一和第二导体的长度分布。

3. 发明授权

US07710789B2 Synchronous address and data multiplexed mode for SRAM 有权
标题翻译： SRAM的同步地址和数据多路复用模式
公开(公告)号：US07710789B2
公开(公告)日：2010-05-04
申请号：US11863164
申请日：2007-09-27
申请人： Tzong-Kwang (Henry) Yeh , Jiann-Jeng (John) Duh , Casey Springer
发明人： Tzong-Kwang (Henry) Yeh , Jiann-Jeng (John) Duh , Casey Springer
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G06F13/4243 , G11C7/1075 , G11C11/413
摘要： A synchronous memory system configurable in a multiplexed or non-multiplexed mode. In the multiplexed mode, address and data are provided on a shared bus, and accesses to the memory system are qualified by memory access control signals, including an address strobe signal, a counter enable signal and a counter repeat signal. A read/write control signal is maintained for one cycle after the last valid access command to avoid bus turn-around problems. In the multiplexed mode, chip enable and output enable signals may be constantly activated, thereby simplifying associated printed circuit board design. Different ports of the synchronous memory system can be independently configured to operate in either the multiplexed or non-multiplexed mode.
摘要翻译：一种以复用或非复用模式配置的同步存储器系统。在多路复用模式下，地址和数据被提供在共享总线上，并且对存储器系统的访问由存储器访问控制信号限定，包括地址选通信号，计数器使能信号和计数器重复信号。在最后的有效访问命令之后，读/写控制信号保持一个周期，以避免总线转向问题。在多路复用模式下，芯片使能和输出使能信号可能会不断激活，从而简化了相关的印刷电路板设计。同步存储器系统的不同端口可以被独立地配置为以多路复用或非复用模式操作。

4. 发明申请

US20100031073A1 SYSTEMS AND METHODS FOR POWER MANAGEMENT IN ELECTRONIC DEVICES 有权
标题翻译：电子设备电源管理系统与方法
公开(公告)号：US20100031073A1
公开(公告)日：2010-02-04
申请号：US12184987
申请日：2008-08-01
申请人： Tzong-Kwang Henry Yeh , Tak Kwong Wong
发明人： Tzong-Kwang Henry Yeh , Tak Kwong Wong
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： Systems and methods are disclosed for managing power consumption in electronic devices. In certain embodiments, an integrated circuit for managing power consumption in an electronic device includes an input/output (I/O) interface, a first circuit block coupled to the I/O interface, and an interface circuit coupled between the I/O interface and the first circuit block, the interface circuit configured to provide a defined logic state to the first circuit block or a second circuit block external to the integrated circuit if one of the first circuit block or the second circuit block is powered down. By providing a defined logic state to the first circuit block or the second circuit block when one of the first circuit block or the second circuit block is powered down, power consumption of the electronic device may be reduced.
摘要翻译：公开了用于管理电子设备中的功耗的系统和方法。在某些实施例中，用于管理电子设备中的功耗的集成电路包括输入/输出（I / O）接口，耦合到I / O接口的第一电路块，以及耦合在I / O接口以及所述第一电路块，所述接口电路被配置为：如果所述第一电路块或所述第二电路块中的一个被掉电，则将限定的逻辑状态提供给所述第一电路块或所述集成电路外部的第二电路块。当第一电路块或第二电路块中的一个被断电时，通过向第一电路块或第二电路块提供定义的逻辑状态，可以减少电子设备的功耗。

5. 发明申请

US20090089538A1 Synchronous Address And Data Multiplexed Mode For SRAM 有权
标题翻译： SRAM的同步地址和数据复用模式
公开(公告)号：US20090089538A1
公开(公告)日：2009-04-02
申请号：US11863164
申请日：2007-09-27
申请人： Tzong-Kwang (Henry) YEH , Jiann-Jeng (John) DUH , Casey SPRINGER
发明人： Tzong-Kwang (Henry) YEH , Jiann-Jeng (John) DUH , Casey SPRINGER
IPC分类号： G06F12/00
CPC分类号： G06F13/4243 , G11C7/1075 , G11C11/413
摘要： A synchronous memory system configurable in a multiplexed or non-multiplexed mode. In the multiplexed mode, address and data are provided on a shared bus, and accesses to the memory system are qualified by memory access control signals, including an address strobe signal, a counter enable signal and a counter repeat signal. A read/write control signal is maintained for one cycle after the last valid access command to avoid bus turn-around problems. In the multiplexed mode, chip enable and output enable signals may be constantly activated, thereby simplifying associated printed circuit board design. Different ports of the synchronous memory system can be independently configured to operate in either the multiplexed or non-multiplexed mode.
摘要翻译：一种以复用或非复用模式配置的同步存储器系统。在多路复用模式下，地址和数据被提供在共享总线上，并且对存储器系统的访问由存储器访问控制信号限定，包括地址选通信号，计数器使能信号和计数器重复信号。在最后的有效访问命令之后，读/写控制信号保持一个周期，以避免总线转向问题。在多路复用模式下，芯片使能和输出使能信号可能会不断激活，从而简化了相关的印刷电路板设计。同步存储器系统的不同端口可以被独立地配置为以多路复用或非复用模式操作。

6. 发明授权

US08892930B2 Systems and methods for power management in electronic devices 有权
标题翻译：电子设备电源管理系统和方法
公开(公告)号：US08892930B2
公开(公告)日：2014-11-18
申请号：US12184987
申请日：2008-08-01
申请人： Tzong-Kwang Henry Yeh , Tak Kwong Wong
发明人： Tzong-Kwang Henry Yeh , Tak Kwong Wong
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： Systems and methods are disclosed for managing power consumption in electronic devices. In certain embodiments, an integrated circuit for managing power consumption in an electronic device includes an input/output (I/O) interface, a first circuit block coupled to the I/O interface, and an interface circuit coupled between the I/O interface and the first circuit block, the interface circuit configured to provide a defined logic state to the first circuit block or a second circuit block external to the integrated circuit if one of the first circuit block or the second circuit block is powered down. By providing a defined logic state to the first circuit block or the second circuit block when one of the first circuit block or the second circuit block is powered down, power consumption of the electronic device may be reduced.
摘要翻译：公开了用于管理电子设备中的功耗的系统和方法。在某些实施例中，用于管理电子设备中的功耗的集成电路包括输入/输出（I / O）接口，耦合到I / O接口的第一电路块，以及耦合在I / O接口以及所述第一电路块，所述接口电路被配置为：如果所述第一电路块或所述第二电路块中的一个被掉电，则将限定的逻辑状态提供给所述第一电路块或所述集成电路外部的第二电路块。当第一电路块或第二电路块中的一个被断电时，通过向第一电路块或第二电路块提供定义的逻辑状态，可以减少电子设备的功耗。

7. 发明授权

US6101116A Six transistor content addressable memory cell 有权
标题翻译：六个晶体管内容可寻址存储单元
公开(公告)号：US6101116A
公开(公告)日：2000-08-08
申请号：US345224
申请日：1999-06-30
申请人： Chuen-Der Lien , Chau-Chin Wu , Tzong-Kwang Henry Yeh
发明人： Chuen-Der Lien , Chau-Chin Wu , Tzong-Kwang Henry Yeh
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G11C15/04
摘要： A six transistor content addressable memory (CAM) cell that prevents disturb of non-written rows during a write operation. The CAM cell comprises an SRAM cell having a pair of cross-coupled inverters and a pair of access transistors. The SRAM cell stores a data value at the output node of one of the inverters and an inverse data value at the output node of the other one of the inverters. An access transistor is connected between each output node and a match line. The match line is connected across the access transistors such that the match line is coupled to the output nodes of the inverters when the access transistors are turned on. Data lines are connected to the gates of the access transistors, and are coupled to receive a data value and an inverse data value. The 6-T CAM cell of this embodiment can be coupled to a plurality of identical 6-T CAM cells to form an array. Each row of CAM cells is coupled to the same match line. Data values are written to and compared with data values stored within each CAM cell. A match condition is sensed on the match line. This 6-T CAM cell is therefore available for reliable use in a storage array. An additional benefit of the 6-T CAM cell is the small cell area due to the small number of transistors.
摘要翻译：六个晶体管内容可寻址存储器（CAM）单元，用于防止写入操作期间非写入行的干扰。 CAM单元包括具有一对交叉耦合的反相器和一对存取晶体管的SRAM单元。 SRAM单元在其中一个逆变器的输出节点处存储数据值，另一个反相器的输出节点存储逆数据值。在每个输出节点和匹配线之间连接一个存取晶体管。匹配线连接在存取晶体管两端，使得当存取晶体管导通时，匹配线耦合到反相器的输出节点。数据线连接到存取晶体管的栅极，并被耦合以接收数据值和逆数据值。该实施例的6-T CAM单元可以耦合到多个相同的6-T CAM单元以形成阵列。每一行CAM单元被耦合到相同的匹配线。将数据值写入并与存储在每个CAM单元内的数据值进行比较。在匹配线上感测到匹配条件。因此，这种6-T CAM单元可用于存储阵列中的可靠使用。由于晶体管的数量少，6-T CAM单元的另外一个好处是小区域。

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