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1. 发明申请

US20060277372A1 Systems and methods for monitoring and controlling binary state devices using a memory device 失效
标题翻译：使用存储设备监控和控制二进制状态设备的系统和方法
公开(公告)号：US20060277372A1
公开(公告)日：2006-12-07
申请号：US11503431
申请日：2006-08-10
申请人： Yunsheng Wang , Casey Springer , Tak Wong , Bill Beane
发明人： Yunsheng Wang , Casey Springer , Tak Wong , Bill Beane
IPC分类号： G06F13/28
CPC分类号： G11C7/1075 , G06F13/1663
摘要： A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device. Each bit of the ODR can manipulate the state of a connected external binary device or can be read without changing the state. The memory device may include settable controlling bits and a set of controlled register bits. Setting the one or more controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR.
摘要翻译：静态随机存取存储器（SRAM）包括用于监视外部二进制器件状态的输入读寄存器（IRR）和用于控制外部二进制器件状态的输出驱动寄存器（ODR）。 SRAM可以是多端口设备，用于多个处理器或控制器的访问。 IRR的每一位可以反映连接的外部二进制设备的状态。 ODR的每一位可以操纵连接的外部二进制设备的状态，或者可以在不改变状态的情况下读取。存储器件可以包括可设置的控制位和一组受控寄存器位。设置一个或多个控制位可以定义哪些受控寄存器位与IRR相关联并且与ODR相关联。

2. 发明申请

US20060106989A1 Systems and methods for monitoring and controlling binary state devices using a memory device 有权
标题翻译：使用存储设备监控和控制二进制状态设备的系统和方法
公开(公告)号：US20060106989A1
公开(公告)日：2006-05-18
申请号：US10992428
申请日：2004-11-17
申请人： Yunsheng Wang , Casey Springer , Tak Wong , Bill Beane
发明人： Yunsheng Wang , Casey Springer , Tak Wong , Bill Beane
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G06F13/1663
摘要： A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.
摘要翻译：静态随机存取存储器（SRAM）包括用于监视外部二进制器件状态的输入读寄存器（IRR）和用于控制外部二进制器件状态的输出驱动寄存器（ODR）。 SRAM可以是多端口设备，用于多个处理器或控制器的访问。 IRR的每一位可以反映连接的外部二进制设备的状态，并可以使用标准读取指令读取到连接的处理器。 ODR的每一位可以通过为器件提供SRAM电源电压的路径来操纵连接的外部二进制器件的状态。也可以在不改变连接的外部二进制设备的状态或中断操作的情况下读取ODR的每个位。当设置为正确模式时，用于IRR和ODR的地址可以与SRAM主存储器阵列一起用于标准存储器操作。

3. 发明申请

US20060084354A1 Reversible ball having hyper-elastic properties and safety perforations 审中-公开
标题翻译：具有超弹性和安全穿孔的可逆球
公开(公告)号：US20060084354A1
公开(公告)日：2006-04-20
申请号：US11237836
申请日：2005-09-29
申请人： Tak Wong , Mark Chernick , Webb Nelson
发明人： Tak Wong , Mark Chernick , Webb Nelson
IPC分类号： A63H33/00
CPC分类号： A63H33/00
摘要： A novelty device and the method of covering an object with the device. The device has an elastic casing that defines an internal area. The elastic casing has an external outer surface and an internal inner surface. Perforations extend between the outer surface and inner surface. The outer surface and the inner surface are different from each other, wherein both surfaces are visually and/or tactilely distinct. An aperture of a first diameter is disposed in the elastic casing. The aperture enables the elastic casing to be selectively inverted. The aperture can be elastically stretched to a much greater size. This enables the casing to be easily turned inside out. It also enables the casing to be easily stretched over secondary objects without inhibiting air flow to the covered object.
摘要翻译：一种新颖的设备和使用该设备覆盖对象的方法。该装置具有限定内部区域的弹性外壳。弹性外壳具有外部外表面和内部内表面。穿孔在外表面和内表面之间延伸。外表面和内表面彼此不同，其中两个表面在视觉上和/或触觉上不同。第一直径的孔设置在弹性壳体中。该孔使得弹性外壳能够选择性地倒转。孔可以弹性拉伸到更大的尺寸。这使得外壳容易转入内部。它还使得外壳可以容易地在次级物体上伸展，而不会阻碍空气流向被覆盖的物体。

4. 发明申请

US20050108604A1 Scan chain registers that utilize feedback paths within latch units to support toggling of latch unit outputs during enhanced delay fault testing 有权
标题翻译：扫描链寄存器利用锁存单元内的反馈路径支持在增强延迟故障测试期间切换锁存单元输出
公开(公告)号：US20050108604A1
公开(公告)日：2005-05-19
申请号：US10933772
申请日：2004-09-03
申请人： Tak Wong
发明人： Tak Wong
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/31858 , G01R31/318541
摘要： An integrated circuit device utilizes a serial scan chain register to support efficient reliability testing of internal circuitry that is not readily accessible from the I/O pins of the device. This reliability testing includes the performance of, among other things, delay fault and stuck-at fault testing of elements within the internal circuitry. The scan chain register has scan chain latch units that support a toggle mode of operation. The scan chain register is provided with serial and parallel input ports and serial and parallel output ports. Each of the plurality of scan chain latch units includes a latch element and additional circuit elements that are configured to selectively establish a feedback path in the respective latch unit. This feedback path operates to pass an inversion of a signal at an output of the latch to an input of the latch when the corresponding scan chain latch unit is enabled to support a toggle mode of operation. Thus, if the output of the latch is set to a logic 1 level, then a toggle operation will cause the output of the latch to switch to a logic 0 level and vice versa. Because of the presence of a respective feedback path within each scan chain latch unit, the toggle operation at the output of a scan chain latch unit will be independent of the value of any other output of other scan chain latch units within the scan chain.
摘要翻译：集成电路器件利用串行扫描链寄存器来支持内部电路的高效可靠性测试，该器件不容易从器件的I / O引脚访问。这种可靠性测试包括在内部电路中的元件的延迟故障和卡住故障测试等方面的性能。扫描链寄存器具有支持切换操作模式的扫描链锁定单元。扫描链寄存器配有串行和并行输入端口以及串行和并行输出端口。多个扫描链锁定单元中的每一个包括锁存元件和被配置为在相应的锁存单元中选择性地建立反馈路径的附加电路元件。当对应的扫描链锁定单元被启用以支持切换操作模式时，该反馈路径用于将锁存器的输出处的信号的反相传递到锁存器的输入。因此，如果锁存器的输出被设置为逻辑1电平，则触发操作将导致锁存器的输出切换到逻辑0电平，反之亦然。由于在每个扫描链锁定单元内存在相应的反馈路径，所以在扫描链锁存单元的输出处的触发操作将与扫描链内的其它扫描链锁定单元的任何其他输出的值无关。

5. 发明申请

US20070236249A1 MINIMIZING TIMING SKEW AMONG CHIP LEVEL OUTPUTS FOR REGISTERED OUTPUT SIGNALS 有权
标题翻译：在注册输出信号的芯片级输出中最小化时序轴
公开(公告)号：US20070236249A1
公开(公告)日：2007-10-11
申请号：US11278370
申请日：2006-03-31
申请人： Tak Wong
发明人： Tak Wong
IPC分类号： H03K19/173
CPC分类号： H03K19/01855 , G01R31/318525 , G01R31/318555 , G01R31/318572 , H03K3/356078
摘要： A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads into a pair of output registers that operate in response to the output clock signal. The output registers may be forced to asynchronously route an input signal to an output terminal during a reset mode and during a boundary scan mode. The output registers can include a safety circuit, which prevents pull-up and pull-down devices (which drive the output signal), from turning on at the same time.
摘要翻译：一种同步输出缓冲电路，其有效地将与输出使能操作，边界扫描操作和电压转换相关联的组合逻辑移动到通向响应于输出时钟信号而工作的一对输出寄存器的管道。在复位模式期间和边界扫描模式期间，可能迫使输出寄存器异步地将输入信号路由到输出端。输出寄存器可以包括一个安全电路，可以防止上拉和下拉器件（驱动输出信号）同时导通。

6. 发明申请

US20060101152A1 Statistics engine 审中-公开
标题翻译：统计引擎
公开(公告)号：US20060101152A1
公开(公告)日：2006-05-11
申请号：US11257910
申请日：2005-10-24
申请人： Tzong-Kwang Yeh , Tak Wong , Sunil Kashyap , Trevor Hiatt , Michael Miller
发明人： Tzong-Kwang Yeh , Tak Wong , Sunil Kashyap , Trevor Hiatt , Michael Miller
IPC分类号： G06F15/16
CPC分类号： H04L41/142 , H04L49/90
摘要： A memory system that provides statistical functions is provided. The memory system includes a dual-port memory array where one port is coupled to a statistics processor. The statistics processor can perform statistical analysis on data stored in the dual-port memory array in response to opcode commands received from an external processor.
摘要翻译：提供了提供统计功能的内存系统。存储器系统包括双端口存储器阵列，其中一个端口耦合到统计处理器。统计处理器可以响应于从外部处理器接收的操作码命令，对存储在双端口存储器阵列中的数据执行统计分析。

7. 发明申请

US20060092749A1 Bitline layout in a dual port memory array 审中-公开
标题翻译：双端口存储器阵列中的位线布局
公开(公告)号：US20060092749A1
公开(公告)日：2006-05-04
申请号：US10976642
申请日：2004-10-29
申请人： Tak Wong
发明人： Tak Wong
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C7/02 , G11C7/18 , G11C11/412
摘要： A multi-port memory array according to some embodiments of the present invention includes a first complementary pair of bit lines of length L corresponding to a first port; a second complementary pair of bit lines of length L corresponding to a second port, wherein the first complementary pair of bit lines is interleaved with the second complementary pair of bit lines, and wherein the first complementary pair of bit lines is twisted at L/2 and the second complementary pair of bit lines is twisted at L/4 and 3L/4. The capacitive coupling between a bit line of the first complementary pair of bit lines and each of the bit lines of the second complementary pair of bit lines is therefore the same, resulting in an elimination of the effects of capacitive coupling.
摘要翻译：根据本发明的一些实施例的多端口存储器阵列包括对应于第一端口的长度为L的第一互补对位线; 对应于第二端口的长度为L的第二对互补位线对，其中所述第一互补的位线对与所述第二互补的位线对交错，并且其中所述第一互补的位线对以L / 2扭曲并且第二互补的位线对以L / 4和3L / 4扭曲。因此，第一互补互补对位线的位线与第二互补互补对位线的位线之间的电容耦合相同，从而消除了电容耦合的影响。

8. 发明申请

US20060084355A1 Reversible toy that converts between a ball and a flying disc 审中-公开
标题翻译：在球和飞盘之间转换的可逆玩具
公开(公告)号：US20060084355A1
公开(公告)日：2006-04-20
申请号：US11245327
申请日：2005-10-07
申请人： Tak Wong , Mark Chernick , Webb Nelson
发明人： Tak Wong , Mark Chernick , Webb Nelson
IPC分类号： A63H33/00
CPC分类号： A63H33/00
摘要： A reversible novelty device that can be inverted between a flying disc and a ball. The reversible novelty device has an elastic casing that defines an internal area. The elastic casing has a first surface and a second surface that can be selectively inverted. An aperture of a first diameter is provided in the elastic casing through which the elastic casing can be selectively inverted. The aperture can be elastically stretched to enable features on the first surface and second surface of the elastic casing to easily pass through the aperture without much effort and without incurring damage. One of the features provided is a flange wing that radially extends from the second surface of the elastic casing. The flange wing extends from the elastic casing and allows the device to perform as a flying disc when thrown.
摘要翻译：可以在飞盘和球之间倒转的可逆新颖装置。可逆新颖装置具有限定内部区域的弹性外壳。弹性外壳具有能够选择性地反转的第一表面和第二表面。第一直径的孔设置在弹性壳体中，弹性壳体可以通过弹性壳体有选择地反转。孔可以被弹性拉伸，使得弹性外壳的第一表面和第二表面上的特征能够容易地穿过孔而无需太多的努力并且不会产生损坏。提供的一个特征是从弹性壳体的第二表面径向延伸的凸缘翼。凸缘翼从弹性壳体延伸，并允许该装置在抛出时作为飞盘执行。

9. 发明申请

US20050282459A1 Bubble-squeezing toy 有权
标题翻译：泡泡玩具
公开(公告)号：US20050282459A1
公开(公告)日：2005-12-22
申请号：US10871089
申请日：2004-06-18
申请人： Cecil Chan , Tak Wong , Lin Chan
发明人： Cecil Chan , Tak Wong , Lin Chan
IPC分类号： A63H3/06 , A63H33/28
CPC分类号： A63H3/06
摘要： A bubble-squeezing toy includes a hollow body formed of flexible plastics material having low stretchability and an aperture; a liner formed of flexible plastics material having high stretchability and located within the hollow body and having a portion adjacent to the aperture that can stretch through the aperture to form an external bubble upon squeezing of the body.
摘要翻译：气泡挤压玩具包括由具有低拉伸性和孔径的柔性塑料材料形成的中空体; 由弹性塑料材料形成的衬垫，其具有高的拉伸性并且位于中空本体内并且具有邻近该孔的部分，该部分可以在挤压本体时穿过该孔从而形成外部气泡。

10. 发明申请

US20070234251A1 Data Output Clock Selection Circuit For Quad-Data Rate Interface 有权
标题翻译：四数据速率接口的数据输出时钟选择电路
公开(公告)号：US20070234251A1
公开(公告)日：2007-10-04
申请号：US11278368
申请日：2006-03-31
申请人： Tak Wong
发明人： Tak Wong
IPC分类号： G06F17/50
CPC分类号： G06F1/10 , H03K5/135
摘要： A method for selecting a data output clock signal includes providing a complementary output clock signal pair to a combinational logic circuit, thereby generating a reset control signal. The reset control signal is activated if the complementary output clock signals have different values, and deactivated if these clock signals have the same predetermined value. The activated reset control signal asynchronously resets a pair of series connected flip-flops. The deactivated reset control signal enables the flip-flops to synchronously propagate a fixed logic signal in response to a clock signal of a complementary input clock signal pair. The output signal of the series-connected flip-flops is used to select the data output clock signal from the first complementary clock signal pair and the second complementary clock signal pair.
摘要翻译：用于选择数据输出时钟信号的方法包括向组合逻辑电路提供互补输出时钟信号对，由此产生复位控制信号。如果互补输出时钟信号具有不同的值，则复位控制信号被激活，如果这些时钟信号具有相同的预定值，则其被禁用。激活的复位控制信号异步复位一对串联连接的触发器。去激活的复位控制信号使触发器响应于互补输入时钟信号对的时钟信号同步地传播固定逻辑信号。串联触发器的输出信号用于从第一互补时钟信号对和第二互补时钟信号对选择数据输出时钟信号。

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