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    • 1. 发明申请
    • Systems and methods for monitoring and controlling binary state devices using a memory device
    • 使用存储设备监控和控制二进制状态设备的系统和方法
    • US20060277372A1
    • 2006-12-07
    • US11503431
    • 2006-08-10
    • Yunsheng WangCasey SpringerTak WongBill Beane
    • Yunsheng WangCasey SpringerTak WongBill Beane
    • G06F13/28
    • G11C7/1075G06F13/1663
    • A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device. Each bit of the ODR can manipulate the state of a connected external binary device or can be read without changing the state. The memory device may include settable controlling bits and a set of controlled register bits. Setting the one or more controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR.
    • 静态随机存取存储器(SRAM)包括用于监视外部二进制器件状态的输入读寄存器(IRR)和用于控制外部二进制器件状态的输出驱动寄存器(ODR)。 SRAM可以是多端口设备,用于多个处理器或控制器的访问。 IRR的每一位可以反映连接的外部二进制设备的状态。 ODR的每一位可以操纵连接的外部二进制设备的状态,或者可以在不改变状态的情况下读取。 存储器件可以包括可设置的控制位和一组受控寄存器位。 设置一个或多个控制位可以定义哪些受控寄存器位与IRR相关联并且与ODR相关联。
    • 2. 发明申请
    • Systems and methods for monitoring and controlling binary state devices using a memory device
    • 使用存储设备监控和控制二进制状态设备的系统和方法
    • US20060106989A1
    • 2006-05-18
    • US10992428
    • 2004-11-17
    • Yunsheng WangCasey SpringerTak WongBill Beane
    • Yunsheng WangCasey SpringerTak WongBill Beane
    • G06F12/00
    • G11C7/1075G06F13/1663
    • A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.
    • 静态随机存取存储器(SRAM)包括用于监视外部二进制器件状态的输入读寄存器(IRR)和用于控制外部二进制器件状态的输出驱动寄存器(ODR)。 SRAM可以是多端口设备,用于多个处理器或控制器的访问。 IRR的每一位可以反映连接的外部二进制设备的状态,并可以使用标准读取指令读取到连接的处理器。 ODR的每一位可以通过为器件提供SRAM电源电压的路径来操纵连接的外部二进制器件的状态。 也可以在不改变连接的外部二进制设备的状态或中断操作的情况下读取ODR的每个位。 当设置为正确模式时,用于IRR和ODR的地址可以与SRAM主存储器阵列一起用于标准存储器操作。
    • 3. 发明授权
    • Systems and methods for monitoring and controlling binary state devices using a memory device
    • 使用存储设备监控和控制二进制状态设备的系统和方法
    • US07904667B2
    • 2011-03-08
    • US11503431
    • 2006-08-10
    • Yunsheng WangCasey SpringerTak Kwong WongBill Beane
    • Yunsheng WangCasey SpringerTak Kwong WongBill Beane
    • G06F13/20
    • G11C7/1075G06F13/1663
    • A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device. Each bit of the ODR can manipulate the state of a connected external binary device or can be read without changing the state. The memory device may include settable controlling bits and a set of controlled register bits. Setting the one or more controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR.
    • 静态随机存取存储器(SRAM)包括用于监视外部二进制器件状态的输入读寄存器(IRR)和用于控制外部二进制器件状态的输出驱动寄存器(ODR)。 SRAM可以是多端口设备,用于多个处理器或控制器的访问。 IRR的每一位可以反映连接的外部二进制设备的状态。 ODR的每一位可以操纵连接的外部二进制设备的状态,或者可以在不改变状态的情况下读取。 存储器件可以包括可设置的控制位和一组受控寄存器位。 设置一个或多个控制位可以定义哪些受控寄存器位与IRR相关联并且与ODR相关联。
    • 4. 发明授权
    • Systems and methods for monitoring and controlling binary state devices using a memory device
    • 使用存储设备监控和控制二进制状态设备的系统和方法
    • US07747828B2
    • 2010-06-29
    • US10992428
    • 2004-11-17
    • Yunsheng WangCasey SpringerTak Kwong WongBill Beane
    • Yunsheng WangCasey SpringerTak Kwong WongBill Beane
    • G06F13/20
    • G11C7/1075G06F13/1663
    • A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.
    • 静态随机存取存储器(SRAM)包括用于监视外部二进制器件状态的输入读寄存器(IRR)和用于控制外部二进制器件状态的输出驱动寄存器(ODR)。 SRAM可以是多端口设备,用于多个处理器或控制器的访问。 IRR的每一位可以反映连接的外部二进制设备的状态,并可以使用标准读取指令读取到连接的处理器。 ODR的每一位可以通过为器件提供SRAM电源电压的路径来操纵连接的外部二进制器件的状态。 也可以在不改变连接的外部二进制设备的状态或中断操作的情况下读取ODR的每个位。 当设置为正确模式时,用于IRR和ODR的地址可以与SRAM主存储器阵列一起用于标准存储器操作。
    • 5. 发明授权
    • Synchronous address and data multiplexed mode for SRAM
    • SRAM的同步地址和数据多路复用模式
    • US07710789B2
    • 2010-05-04
    • US11863164
    • 2007-09-27
    • Tzong-Kwang (Henry) YehJiann-Jeng (John) DuhCasey Springer
    • Tzong-Kwang (Henry) YehJiann-Jeng (John) DuhCasey Springer
    • G11C7/10G11C8/00
    • G06F13/4243G11C7/1075G11C11/413
    • A synchronous memory system configurable in a multiplexed or non-multiplexed mode. In the multiplexed mode, address and data are provided on a shared bus, and accesses to the memory system are qualified by memory access control signals, including an address strobe signal, a counter enable signal and a counter repeat signal. A read/write control signal is maintained for one cycle after the last valid access command to avoid bus turn-around problems. In the multiplexed mode, chip enable and output enable signals may be constantly activated, thereby simplifying associated printed circuit board design. Different ports of the synchronous memory system can be independently configured to operate in either the multiplexed or non-multiplexed mode.
    • 一种以复用或非复用模式配置的同步存储器系统。 在多路复用模式下,地址和数据被提供在共享总线上,并且对存储器系统的访问由存储器访问控制信号限定,包括地址选通信号,计数器使能信号和计数器重复信号。 在最后的有效访问命令之后,读/写控制信号保持一个周期,以避免总线转向问题。 在多路复用模式下,芯片使能和输出使能信号可能会不断激活,从而简化了相关的印刷电路板设计。 同步存储器系统的不同端口可以被独立地配置为以多路复用或非复用模式操作。