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1. 发明申请

WO2018125080A1 ENABLING LONG INTERCONNECT BRIDGES 审中-公开
公开(公告)号：WO2018125080A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/068876
申请日：2016-12-28
申请人： INTEL CORPORATION , MAHAJAN, Ravindranath V. , QIAN, Zhiguo , BRAUNISCH, Henning , AYGUN, Kemal , SHARAN, Sujit
发明人： MAHAJAN, Ravindranath V. , BRAUNISCH, Henning , AYGUN, Kemal , SHARAN, Sujit
IPC分类号： H01L23/00 , H01L23/522
摘要： A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.

2. 发明申请

WO2018009167A1 RLINK-ON-DIE INTERCONNECT FEATURES TO ENABLE SIGNALING 审中-公开
标题翻译： RLINK-DIE互连功能使信令生效
公开(公告)号：WO2018009167A1
公开(公告)日：2018-01-11
申请号：PCT/US2016/040907
申请日：2016-07-02
申请人： INTEL CORPORATION , ZHANG, Yu Amos , AYGUN, Kemal
发明人： ZHANG, Yu Amos , AYGUN, Kemal
IPC分类号： H01L23/50 , H01L23/52 , H01L23/522 , H01L23/00 , H01L21/768
CPC分类号： H01L21/76877 , H01L21/76898 , H01L23/50 , H01L23/522 , H01L23/5222 , H01L23/5227
摘要： Integrated circuit (IC) chip "on-die" interconnection features (and methods for their manufacture) may improve signal connections and transmission through a data signal communication channel from one chip, through semiconductor device packaging, and to another component, such as another chip. Such chip interconnection features may include (1) "last silicon metal level (LSML)" data signal "leadway (LDW) routing" traces isolated between LSLM isolation (e.g., power and/or ground) traces to: (2) add a length of the isolated data signal LDW traces to increase a total length of and tune data signal communication channels extending through a package between two communicating chips and (3) create switched buffer (SB) pairs of data signal channels that use the isolated data signal LDW traces to switch the locations of the pairs data signal circuitry and surface contacts for packaging connection bumps.
摘要翻译：集成电路（IC）芯片“片上”（on-die）互连特征（以及用于其制造的方法）可以改善通过数据信号通信信道从一个芯片经过半导体器件封装到另一个组件（例如另一个芯片）的信号连接和传输。这样的芯片互连特征可以包括（1）“最后硅金属层（LSML）” 数据信号“引线（LDW）路由” （2）添加一段长度的隔离数据信号LDW迹线，以增加延伸通过两个通信芯片之间的封装的数据信号通信信道的总长度和调谐数据信号通信信道和（3）创建使用隔离数据信号LDW迹线的切换缓冲器（SB）对数据信号通道来切换数据信号电路和表面触点的位置以用于封装连接凸点。

3. 发明申请

WO2018004619A1 HIGH DENSITY INTERCONNECT STRUCTURES CONFIGURED FOR MANUFACTURING AND PERFORMANCE 审中-公开
标题翻译：配置用于制造和性能的高密度互连结构
公开(公告)号：WO2018004619A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040486
申请日：2016-06-30
申请人： BRAUNISCH, Henning , AYGUN, Kemal , JAIN, Ajay , QIAN, Zhiguo
发明人： BRAUNISCH, Henning , AYGUN, Kemal , JAIN, Ajay , QIAN, Zhiguo
IPC分类号： H01L23/48 , H01L23/00 , H01L23/495 , H01L23/498 , H01L23/522
摘要： Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.
摘要翻译：这里通常讨论的是包括或提供高密度互连结构的方法和设备。高密度互连结构可以包括交替介电层和金属化层的叠层，所述金属化层包括至少三个金属化层，所述至少三个金属化层包括在导电材料之间具有低k介电材料的导电材料，以及至少两个介电层，包括第一介质k介电材料，所述至少两个电介质层位于所述至少三个金属化层的两个金属化层之间，第二介质k电介质材料直接位于所述堆叠的顶表面上，第二通孔延伸穿过所述第二介质k电介质所述第二通孔电连接到所述三个或更多个金属化层的金属化层中的导电材料，所述第二介质k电介质材料上方的焊盘并且电连接到所述第二通孔。

4. 发明申请

WO2017039628A1 INORGANIC INTERPOSER FOR MULTI-CHIP PACKAGING 审中-公开
标题翻译：无芯插件多芯片包装
公开(公告)号：WO2017039628A1
公开(公告)日：2017-03-09
申请号：PCT/US2015/047811
申请日：2015-08-31
申请人： SOBIESKI, Daniel , DARMAWIKARTA, Kristof , BOYAPATI, Sri Ranga Sai , CELIKKOL, Merve , LEE, Kyu Oh , AYGUN, Kemal , QIAN, Zhiguo
发明人： SOBIESKI, Daniel , DARMAWIKARTA, Kristof , BOYAPATI, Sri Ranga Sai , CELIKKOL, Merve , LEE, Kyu Oh , AYGUN, Kemal , QIAN, Zhiguo
IPC分类号： H01L25/065 , H01L25/18
CPC分类号： H01L25/18 , H01L23/147 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L25/0655 , H01L2224/16227 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/15313 , H01L2924/157 , H01L2924/3511
摘要： Discussed generally herein are methods and devices for multichip packages that include an inorganic interposer. A device can include a substrate including low density interconnect circuitry therein, an inorganic interposer on the substrate, the inorganic interposer including high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including inorganic materials, and two or more chips electrically connected to the inorganic interposer, the two or more chips electrically connected to each other through the high density interconnect circuitry.
摘要翻译：这里通常讨论的是包括无机插入物的多芯片封装的方法和装置。器件可以包括其中包括低密度互连电路的衬底，衬底上的无机插入器，无机插入器包括电连接到低密度互连电路的高密度互连电路，无机插入器包括无机材料，以及两个或更多个芯片连接到无机插入器，两个或更多芯片通过高密度互连电路彼此电连接。

5. 发明申请

WO2016048352A1 SOCKET CONTACT TECHNIQUES AND CONFIGURATIONS 审中-公开
标题翻译：插座联系技术和配置
公开(公告)号：WO2016048352A1
公开(公告)日：2016-03-31
申请号：PCT/US2014/057686
申请日：2014-09-26
申请人： INTEL CORPORATION , ATHREYA, Dhanya , CHAWLA, Gaurav , AYGUN, Kemal , HEPPNER, Joshua D. , NEKKANTY, Srikant , SMALLEY, Jeffory L. , CANNY, Sarah M. , GORDON, Glen P. , GARCIA, Michael
发明人： ATHREYA, Dhanya , CHAWLA, Gaurav , AYGUN, Kemal , HEPPNER, Joshua D. , NEKKANTY, Srikant , SMALLEY, Jeffory L. , CANNY, Sarah M. , GORDON, Glen P. , GARCIA, Michael
IPC分类号： H01R33/76 , H01L23/32
CPC分类号： H01R33/7685 , H01L23/32 , H01L23/49827 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例针对套接触接触技术和配置。在一个实施例中，装置可以包括具有第一侧和与第一侧相对设置的第二侧的插座衬底，通过插座衬底形成的开口，设置在开口中并被配置为在第一所述电接触件具有延伸超过所述第一侧面的悬臂部分，其中所述开口中的所述插座基板的所述第一侧面和所述表面镀有金属。可以描述和/或要求保护其他实施例。

6. 发明申请

WO2010036676A3 INPUT/OUTPUT ARCHITECTURE FOR MOUNTED PROCESSORS, AND METHODS OF USING SAME 审中-公开
标题翻译：用于安装处理器的输入/输出结构，以及使用该结构的方法
公开(公告)号：WO2010036676A3
公开(公告)日：2010-07-22
申请号：PCT/US2009057968
申请日：2009-09-23
申请人： INTEL CORP , GANESAN SANKA , AYGUN KEMAL , RAMASWAMY CHANDRASHEKHAR , PALMER ERIC , BRAUNISCH HENNING
发明人： GANESAN SANKA , AYGUN KEMAL , RAMASWAMY CHANDRASHEKHAR , PALMER ERIC , BRAUNISCH HENNING
IPC分类号： H01L23/48 , H01L23/488
CPC分类号： H01L23/34 , H01L23/367 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L23/66 , H01L2223/6627 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00014 , H01L2924/15192 , H01L2924/19032 , H01L2224/0401
摘要： A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
摘要翻译：高速I / O走线是集成电路封装基板的I / O封装体系结构的一部分。集成电路封装衬底包括在管芯侧上的集成散热器覆盖区和I / O迹线，以与IC器件耦合以设置在IHS覆盖区内。 I / O走线包括一个位于IHS占位面积之外的引出端子，用于耦合IC设备以放置在IHS占用面积之外。高速I / O跟踪可以支持从每秒5千兆位（Gb / s）到40 Gb / s范围内的处理器的数据流速。

7. 发明申请

WO2018009171A1 RLINK - DIE TO DIE CHANNEL INTERCONNECT CONFIGURATIONS TO IMPROVE SIGNALING 审中-公开
标题翻译： RLINK - 模切通道互连配置以改善信号传输
公开(公告)号：WO2018009171A1
公开(公告)日：2018-01-11
申请号：PCT/US2016/040912
申请日：2016-07-02
申请人： INTEL CORPORATION , AYGUN, Kemal , DISCHLER, Richard J. , MORRISS, Jeff C. , QIAN, Zhiguo , GOMES, Wilfred , ZHANG, Yu Amos , VISWANATH, Ram S. , SWAMINATHAN, Rajasekaran Raja , SRINIVASAN, Sriram , MEKONNEN, Yidnekachew S. , GANESAN, Sanka Gans , ROYTMAN, Eduard , MANUSHAROW, Mathew J.
发明人： AYGUN, Kemal , DISCHLER, Richard J. , MORRISS, Jeff C. , QIAN, Zhiguo , GOMES, Wilfred , ZHANG, Yu Amos , VISWANATH, Ram S. , SWAMINATHAN, Rajasekaran Raja , SRINIVASAN, Sriram , MEKONNEN, Yidnekachew S. , GANESAN, Sanka Gans , ROYTMAN, Eduard , MANUSHAROW, Mathew J.
IPC分类号： H01L25/065 , H01L23/60 , H01L23/498 , H01L23/525 , H01L23/00
摘要： Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
摘要翻译：集成电路（IC）芯片裸片至裸片通道互连配置（用于其制造的系统及方法）可通过包括裸片上导入结构来改善进入并通过单端总线数据信号通信通道的信号传输; 片上互连功能; 封装内第一级裸片凸点设计和地面织带结构; 封装式高速水平数据信号传输线; 封装上垂直数据信号传输互连; 和/或封装内电光（EO）连接器，用于改进信号连接和通过延伸穿过一个或多个半导体器件封装器件的数据信号通道的传输，所述半导体器件封装器件可包括电光（EO））连接器，在该连接器上可以安装至少一个封装器件，和/或作为半导体器件封装在封装式封装配置中。

8. 发明申请

WO2010036676A2 INPUT/OUTPUT ARCHITECTURE FOR MOUNTED PROCESSORS, AND METHODS OF USING SAME 审中-公开
标题翻译：用于安装处理器的输入/输出结构，以及使用它们的方法
公开(公告)号：WO2010036676A2
公开(公告)日：2010-04-01
申请号：PCT/US2009/057968
申请日：2009-09-23
申请人： INTEL CORPORATION , GANESAN, Sanka , AYGUN, Kemal , RAMASWAMY, Chandrashekhar , PALMER, Eric , BRAUNISCH, Henning
发明人： GANESAN, Sanka , AYGUN, Kemal , RAMASWAMY, Chandrashekhar , PALMER, Eric , BRAUNISCH, Henning
IPC分类号： H01L23/48 , H01L23/488
CPC分类号： H01L23/34 , H01L23/367 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L23/66 , H01L2223/6627 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H01L2924/19032 , H01L2224/0401
摘要： A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
摘要翻译：高速I / O迹线是集成电路封装基板的I / O封装架构的一部分。集成电路封装衬底包括在芯片侧的集成的散热器占地面积，并且I / O迹线与要设置在IHS占地面积内的IC器件耦合。 I / O跟踪包括IHS封装之外的引脚输出端子，以连接到要设置在IHS占用空间之外的IC器件。高速I / O跟踪可以维持从5吉比特每秒（Gb / s）到40 Gb / s的处理器的数据流速。

9. 发明申请

WO2018063197A1 INTERCONNECTOR WITH BUNDLED INTERCONNECTS 审中-公开
标题翻译： INTERCONNECTOR与束缚的互连
公开(公告)号：WO2018063197A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054235
申请日：2016-09-28
申请人： BRAUNISCH, Henning , AYGUN, Kemal , MEKONNEN, Yidnekachew S.
发明人： BRAUNISCH, Henning , AYGUN, Kemal , MEKONNEN, Yidnekachew S.
IPC分类号： H01L25/18 , H01L23/498 , H01L25/065
CPC分类号： H01L23/5381 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L23/66 , H01L25/065 , H01L25/18 , H01L2224/16235 , H01L2924/15192
摘要： Disclosed is a signaling system. The signaling system may comprise a transmitter, a receiver, and a package interconnect. The transmitter may be configured to transmit M signals. The receiver may be configured to receive the M signals. The package interconnect may include a bundle of N wires electrically connecting the transmitter and the receiver. During operation, the N wires may be electromagnetically coupled with each other and the M signals may travel between the transmitter and the receiver on the bundle of N wires.
摘要翻译：公开了一种信令系统。信令系统可以包括发射机，接收机和封装互连。发射机可以被配置为发送M个信号。接收器可以被配置为接收M个信号。封装互连可以包括电连接发射器和接收器的N束导线。在操作期间，N根导线可以彼此电磁耦合，并且M个信号可以在N根导线束上在发射器和接收器之间传播。

10. 发明申请

WO2007070356A2 PACKAGE USING ARRAY CAPACITOR CORE 审中-公开
标题翻译：封装使用阵列电容器核心
公开(公告)号：WO2007070356A2
公开(公告)日：2007-06-21
申请号：PCT/US2006046776
申请日：2006-12-06
申请人： INTEL CORP , EILERT KIMBERLY D , RADHAKRISHNAN KALADHAR , AYGUN KEMAL , HILL MICHAEL J
发明人： EILERT KIMBERLY D , RADHAKRISHNAN KALADHAR , AYGUN KEMAL , HILL MICHAEL J
IPC分类号： H01L21/48 , H01L23/498 , H01L23/64
CPC分类号： H01L23/49822 , H01L21/4857 , H01L21/6835 , H01L23/50 , H01L23/66 , H01L24/81 , H01L24/97 , H01L2221/68345 , H01L2224/16 , H01L2224/81191 , H01L2224/8121 , H01L2224/81815 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01075 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H05K1/142 , H05K1/162 , H05K3/007 , H05K3/4602 , H05K3/4614 , H05K2201/09309 , H05K2203/0156 , H05K2203/061 , H01L2924/00
摘要： An embodiment of the present invention is a technique to fabricate a package substrate. The package substrate includes top substrate layers, an array capacitor, and bottom substrate layers. The top substrate layers embed micro-vias. The micro-vias have a micro- via area and provide electrical connections between the top substrate layers. The array capacitor structure is placed in contact with the micro-via area. The array capacitor structure is electrically connected to the micro- vias. The bottom substrate layers are formed on the array capacitor structure.
摘要翻译：本发明的实施例是制造封装衬底的技术。封装衬底包括顶部衬底层，阵列电容器和底部衬底层。顶部衬底层嵌入微通孔。微通道具有微通道区域并提供顶部衬底层之间的电连接。阵列电容器结构被放置成与微通孔区域接触。阵列电容器结构电连接到微通孔。底部衬底层形成在阵列电容器结构上。

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