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1. 发明申请

WO2018125080A1 ENABLING LONG INTERCONNECT BRIDGES 审中-公开
公开(公告)号：WO2018125080A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/068876
申请日：2016-12-28
申请人： INTEL CORPORATION , MAHAJAN, Ravindranath V. , QIAN, Zhiguo , BRAUNISCH, Henning , AYGUN, Kemal , SHARAN, Sujit
发明人： MAHAJAN, Ravindranath V. , BRAUNISCH, Henning , AYGUN, Kemal , SHARAN, Sujit
IPC分类号： H01L23/00 , H01L23/522
摘要： A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.

2. 发明申请

WO2018004619A1 HIGH DENSITY INTERCONNECT STRUCTURES CONFIGURED FOR MANUFACTURING AND PERFORMANCE 审中-公开
标题翻译：配置用于制造和性能的高密度互连结构
公开(公告)号：WO2018004619A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040486
申请日：2016-06-30
申请人： BRAUNISCH, Henning , AYGUN, Kemal , JAIN, Ajay , QIAN, Zhiguo
发明人： BRAUNISCH, Henning , AYGUN, Kemal , JAIN, Ajay , QIAN, Zhiguo
IPC分类号： H01L23/48 , H01L23/00 , H01L23/495 , H01L23/498 , H01L23/522
摘要： Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.
摘要翻译：这里通常讨论的是包括或提供高密度互连结构的方法和设备。高密度互连结构可以包括交替介电层和金属化层的叠层，所述金属化层包括至少三个金属化层，所述至少三个金属化层包括在导电材料之间具有低k介电材料的导电材料，以及至少两个介电层，包括第一介质k介电材料，所述至少两个电介质层位于所述至少三个金属化层的两个金属化层之间，第二介质k电介质材料直接位于所述堆叠的顶表面上，第二通孔延伸穿过所述第二介质k电介质所述第二通孔电连接到所述三个或更多个金属化层的金属化层中的导电材料，所述第二介质k电介质材料上方的焊盘并且电连接到所述第二通孔。

3. 发明申请

WO2006039640A1 CONNECTORIZATION PROCESS FOR OPTICAL CHIP-TO-CHIP INTERCONNECTS 审中-公开
标题翻译：光纤到芯片互连的连接过程
公开(公告)号：WO2006039640A1
公开(公告)日：2006-04-13
申请号：PCT/US2005/035473
申请日：2005-09-29
申请人： INTEL CORPORATION , TOWLE, Steven , LU, Daoqiang , BRAUNISCH, Henning
发明人： TOWLE, Steven , LU, Daoqiang , BRAUNISCH, Henning
IPC分类号： G02B6/30 , G02B6/36 , G02B6/42
CPC分类号： G02B6/241 , G02B6/30
摘要： An optical package (100) comprising an optoelectric element (104) and a substrate (102) having a trench (214) therein, the trench (214) extending to an edge of the substrate (102), a waveguide array (114) positioned in the trench (214), the waveguide array (114) extending to the edge of the substrate (102), and a lid (216) attached or near the edge (116) of the substrate (102) and spanning a width of the waveguide array (114), the lid (116) including a recess (404) having a bottom (406), wherein the bottom (406) is in direct contact with a surface (704) of the waveguide array (114). The lid (116) and the substrate (102) form a connector (118) for optically connecting the optical package (100) to other components.
摘要翻译：一种包括光电元件（104）和其中具有沟槽（214）的衬底（102）的光学封装（100），所述沟槽（214）延伸到衬底（102）的边缘，波导阵列（114）在所述沟槽（214）中，所述波导阵列（114）延伸到所述衬底（102）的边缘，以及盖（216），其附接或靠近所述衬底（102）的边缘（116）并跨越所述衬底波导阵列（114），所述盖（116）包括具有底部（406）的凹部（404），其中所述底部（406）与所述波导阵列（114）的表面（704）直接接触。盖（116）和基板（102）形成用于将光学封装（100）光学连接到其它部件的连接器（118）。

4. 发明申请

WO2013074122A1 THERMAL MANAGEMENT IN PACKAGED VCSELS 审中-公开
标题翻译：包装VCSELS中的热管理
公开(公告)号：WO2013074122A1
公开(公告)日：2013-05-23
申请号：PCT/US2011/061423
申请日：2011-11-18
申请人： INTEL CORPORATION , EID, Feras , LIFF, Shawna M. , BRAUNISCH, Henning
发明人： EID, Feras , LIFF, Shawna M. , BRAUNISCH, Henning
IPC分类号： H01S5/024 , H01S3/04 , H01S5/183
CPC分类号： H01S5/02476 , H01S5/02236 , H01S5/183 , H01S5/423
摘要： Heat management systems for vertical cavity surface emitting laser (VCSEL) chips are provided. Embodiments of the invention provide substrates having a vertical cavity surface emitting laser chip disposed on the substrate surface and electrically interconnected with the substrate, a thermal frame disposed on the substrate surface and proximate to at least three sides of the vertical cavity surface emitting laser chip, and a thermal interface material disposed between the at least three sides of the vertical cavity surface emitting laser chip and the thermal frame. The substrate can also include a transceiver chip that is operably coupled to a further integrated circuit chip and that is capable of driving the VCSEL chip.
摘要翻译：提供了垂直腔表面发射激光（VCSEL）芯片的热管理系统。本发明的实施例提供了具有设置在衬底表面上并与衬底电互连的垂直腔表面发射激光器芯片的衬底，设置在衬底表面上并且靠近垂直腔表面发射激光器芯片的至少三个侧面的热框架，以及设置在垂直腔表面发射激光芯片和热框架的至少三个侧面之间的热界面材料。衬底还可以包括可操作地耦合到另一集成电路芯片并且能够驱动VCSEL芯片的收发器芯片。

5. 发明申请

WO2010151350A1 MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS IN SAME 审中-公开
标题翻译：多芯片封装及其相互之间提供DIE-TO-DIE互连的方法
公开(公告)号：WO2010151350A1
公开(公告)日：2010-12-29
申请号：PCT/US2010/027035
申请日：2010-03-11
申请人： INTEL CORPORATION , BRAUNISCH, Henning , CHIU, Chia-Pin , ALEKSOV, Aleksandar , AU, Hinment , LOTZ, Stefanie M. , SWAN, Johanna M. , SHARAN, Sujit
发明人： BRAUNISCH, Henning , CHIU, Chia-Pin , ALEKSOV, Aleksandar , AU, Hinment , LOTZ, Stefanie M. , SWAN, Johanna M. , SHARAN, Sujit
IPC分类号： H01L23/48
CPC分类号： H01L23/5385 , H01L21/6835 , H01L23/13 , H01L24/14 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/13099 , H01L2224/1403 , H01L2224/141 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32245 , H01L2224/45099 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73207 , H01L2224/73253 , H01L2224/81001 , H01L2224/81005 , H01L2224/81801 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01076 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/12042 , H01L2924/1461 , H01L2924/15153 , H01L2924/19107 , H01L2924/351 , H01L2924/00
摘要： A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
摘要翻译：多芯片封装包括具有第一侧面（111），相对的第二侧面（112）和从第一侧向第二侧延伸的第三侧面（213）的基板（110），第一模具（120））和附接到所述基板的第一侧的第二模具（130），以及邻近所述基板的第三侧并连接到所述第一模具和所述第二模具的桥接件（140）。基板的任何部分都不在桥下。该桥在第一管芯和第二管芯之间形成连接。或者，桥可以设置在衬底中的空腔（615,915）中，或者设置在衬底和裸片层（750）之间。该桥可以构成一个有源管芯，并且可以使用引线键连接到衬底（241,841,1141,1541）。

6. 发明申请

WO2010036676A2 INPUT/OUTPUT ARCHITECTURE FOR MOUNTED PROCESSORS, AND METHODS OF USING SAME 审中-公开
标题翻译：用于安装处理器的输入/输出结构，以及使用它们的方法
公开(公告)号：WO2010036676A2
公开(公告)日：2010-04-01
申请号：PCT/US2009/057968
申请日：2009-09-23
申请人： INTEL CORPORATION , GANESAN, Sanka , AYGUN, Kemal , RAMASWAMY, Chandrashekhar , PALMER, Eric , BRAUNISCH, Henning
发明人： GANESAN, Sanka , AYGUN, Kemal , RAMASWAMY, Chandrashekhar , PALMER, Eric , BRAUNISCH, Henning
IPC分类号： H01L23/48 , H01L23/488
CPC分类号： H01L23/34 , H01L23/367 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L23/66 , H01L2223/6627 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H01L2924/19032 , H01L2224/0401
摘要： A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
摘要翻译：高速I / O迹线是集成电路封装基板的I / O封装架构的一部分。集成电路封装衬底包括在芯片侧的集成的散热器占地面积，并且I / O迹线与要设置在IHS占地面积内的IC器件耦合。 I / O跟踪包括IHS封装之外的引脚输出端子，以连接到要设置在IHS占用空间之外的IC器件。高速I / O跟踪可以维持从5吉比特每秒（Gb / s）到40 Gb / s的处理器的数据流速。

7. 发明申请

WO2008083234A1 SPLIT SOCKET OPTICAL INTERCONNECT 审中-公开
标题翻译：分体插座光学互连
公开(公告)号：WO2008083234A1
公开(公告)日：2008-07-10
申请号：PCT/US2007/088973
申请日：2007-12-27
申请人： INTEL CORPORATION , LU, Daoqiang , ALDUINO, Andrew , BRAUNISCH, Henning
发明人： LU, Daoqiang , ALDUINO, Andrew , BRAUNISCH, Henning
IPC分类号： G02B6/42 , H01L31/0232
CPC分类号： G02B6/4201 , G02B6/4214 , G02B6/4249 , G02B6/4284 , H01L2224/73204 , H01L2224/73253
摘要： A split microprocessor socket is disclosed that provides a cavity created at an outer edge of the microprocessor socket. An optical module may be fitted in the cavity thus providing an optical fiber or waveguide connection directly to the socket. This low cost optical interconnect, closely packaged with the microprocessor, may alleviate bandwidth constraints associated with conventional electrical connections.
摘要翻译：公开了一种分离的微处理器插座，其提供在微处理器插座的外边缘处形成的空腔。光学模块可以安装在空腔中，从而直接向插座提供光纤或波导连接。这种与微处理器紧密封装的低成本光互连可以减轻与传统电连接相关的带宽限制。

8. 发明申请

WO2015047350A1 DUAL-SIDED DIE PACKAGES 审中-公开
标题翻译：双面包装
公开(公告)号：WO2015047350A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/062471
申请日：2013-09-27
申请人： INTEL CORPORATION , BRAUNISCH, Henning , EID, Feras , ELSHERBINI, Adel , SWAN, Johanna, M. , NELSON, Don, W.
发明人： BRAUNISCH, Henning , EID, Feras , ELSHERBINI, Adel , SWAN, Johanna, M. , NELSON, Don, W.
IPC分类号： H01L23/12
CPC分类号： H01L23/3675 , H01L21/52 , H01L23/36 , H01L23/367 , H01L23/3677 , H01L23/473 , H01L23/49811 , H01L23/49833 , H01L23/49838 , H01L23/50 , H01L23/5389 , H01L2924/0002 , H05K1/021 , H05K1/185 , H05K2201/066 , H05K2201/10416 , H05K2201/10545 , H01L2924/00
摘要： An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.
摘要翻译：一种包括模具的设备，所述模具的第一侧包括第一类型的系统级接触点和包括第二类型的接触点的第二侧; 以及耦合到管芯和管芯的第二侧的封装衬底。一种包括管芯的设备，所述管芯的第一侧包括多个系统级逻辑接触点和包括第二多个系统级电力接触点的第二侧。一种方法，包括将管芯的第一侧上的第一类型的系统级接触点中的一个与管芯的第二侧上的第二类型的系统级接触点耦合到封装衬底。

9. 发明申请

WO2010036676A3 INPUT/OUTPUT ARCHITECTURE FOR MOUNTED PROCESSORS, AND METHODS OF USING SAME 审中-公开
标题翻译：用于安装处理器的输入/输出结构，以及使用该结构的方法
公开(公告)号：WO2010036676A3
公开(公告)日：2010-07-22
申请号：PCT/US2009057968
申请日：2009-09-23
申请人： INTEL CORP , GANESAN SANKA , AYGUN KEMAL , RAMASWAMY CHANDRASHEKHAR , PALMER ERIC , BRAUNISCH HENNING
发明人： GANESAN SANKA , AYGUN KEMAL , RAMASWAMY CHANDRASHEKHAR , PALMER ERIC , BRAUNISCH HENNING
IPC分类号： H01L23/48 , H01L23/488
CPC分类号： H01L23/34 , H01L23/367 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L23/66 , H01L2223/6627 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00014 , H01L2924/15192 , H01L2924/19032 , H01L2224/0401
摘要： A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
摘要翻译：高速I / O走线是集成电路封装基板的I / O封装体系结构的一部分。集成电路封装衬底包括在管芯侧上的集成散热器覆盖区和I / O迹线，以与IC器件耦合以设置在IHS覆盖区内。 I / O走线包括一个位于IHS占位面积之外的引出端子，用于耦合IC设备以放置在IHS占用面积之外。高速I / O跟踪可以支持从每秒5千兆位（Gb / s）到40 Gb / s范围内的处理器的数据流速。

10. 发明申请

WO2008083234A9 SPLIT SOCKET OPTICAL INTERCONNECT 审中-公开
标题翻译：分离插座光学互连
公开(公告)号：WO2008083234A9
公开(公告)日：2008-08-14
申请号：PCT/US2007088973
申请日：2007-12-27
申请人： INTEL CORP , LU DAOQIANG , ALDUINO ANDREW , BRAUNISCH HENNING
发明人： LU DAOQIANG , ALDUINO ANDREW , BRAUNISCH HENNING
IPC分类号： G02B6/42 , H01L31/0232
CPC分类号： G02B6/4201 , G02B6/4214 , G02B6/4249 , G02B6/4284 , H01L2224/73204 , H01L2224/73253
摘要： A split microprocessor socket is disclosed that provides a cavity created at an outer edge of the microprocessor socket. An optical module may be fitted in the cavity thus providing an optical fiber or waveguide connection directly to the socket. This low cost optical interconnect, closely packaged with the microprocessor, may alleviate bandwidth constraints associated with conventional electrical connections.
摘要翻译：公开了一种分立微处理器插座，其提供在微处理器插座的外边缘处产生的空腔。可以将光学模块装配在空腔中，从而将光纤或波导连接直接连接到插座。与微处理器紧密封装的这种低成本光互连可以减轻与传统电连接相关联的带宽约束。

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