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1. 发明申请

WO2018182598A1 SIDE MOUNTED INTERCONNECT BRIDGES 审中-公开
公开(公告)号：WO2018182598A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/024803
申请日：2017-03-29
申请人： INTEL CORPORATION , HOSSAIN, MD Altaf , DORAN, Kevin, J. , ZHANG, Yu Amos , QIAN, Zhiguo
发明人： HOSSAIN, MD Altaf , ZHANG, Yu Amos , QIAN, Zhiguo
IPC分类号： H01L25/18 , H01L25/16 , H01L23/538 , H01L25/065 , H01L23/48
摘要： A de vice and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown.

2. 发明申请

WO2018009171A1 RLINK - DIE TO DIE CHANNEL INTERCONNECT CONFIGURATIONS TO IMPROVE SIGNALING 审中-公开
标题翻译： RLINK - 模切通道互连配置以改善信号传输
公开(公告)号：WO2018009171A1
公开(公告)日：2018-01-11
申请号：PCT/US2016/040912
申请日：2016-07-02
申请人： INTEL CORPORATION , AYGUN, Kemal , DISCHLER, Richard J. , MORRISS, Jeff C. , QIAN, Zhiguo , GOMES, Wilfred , ZHANG, Yu Amos , VISWANATH, Ram S. , SWAMINATHAN, Rajasekaran Raja , SRINIVASAN, Sriram , MEKONNEN, Yidnekachew S. , GANESAN, Sanka Gans , ROYTMAN, Eduard , MANUSHAROW, Mathew J.
发明人： AYGUN, Kemal , DISCHLER, Richard J. , MORRISS, Jeff C. , QIAN, Zhiguo , GOMES, Wilfred , ZHANG, Yu Amos , VISWANATH, Ram S. , SWAMINATHAN, Rajasekaran Raja , SRINIVASAN, Sriram , MEKONNEN, Yidnekachew S. , GANESAN, Sanka Gans , ROYTMAN, Eduard , MANUSHAROW, Mathew J.
IPC分类号： H01L25/065 , H01L23/60 , H01L23/498 , H01L23/525 , H01L23/00
摘要： Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
摘要翻译：集成电路（IC）芯片裸片至裸片通道互连配置（用于其制造的系统及方法）可通过包括裸片上导入结构来改善进入并通过单端总线数据信号通信通道的信号传输; 片上互连功能; 封装内第一级裸片凸点设计和地面织带结构; 封装式高速水平数据信号传输线; 封装上垂直数据信号传输互连; 和/或封装内电光（EO）连接器，用于改进信号连接和通过延伸穿过一个或多个半导体器件封装器件的数据信号通道的传输，所述半导体器件封装器件可包括电光（EO））连接器，在该连接器上可以安装至少一个封装器件，和/或作为半导体器件封装在封装式封装配置中。

3. 发明申请

WO2018009167A1 RLINK-ON-DIE INTERCONNECT FEATURES TO ENABLE SIGNALING 审中-公开
标题翻译： RLINK-DIE互连功能使信令生效
公开(公告)号：WO2018009167A1
公开(公告)日：2018-01-11
申请号：PCT/US2016/040907
申请日：2016-07-02
申请人： INTEL CORPORATION , ZHANG, Yu Amos , AYGUN, Kemal
发明人： ZHANG, Yu Amos , AYGUN, Kemal
IPC分类号： H01L23/50 , H01L23/52 , H01L23/522 , H01L23/00 , H01L21/768
CPC分类号： H01L21/76877 , H01L21/76898 , H01L23/50 , H01L23/522 , H01L23/5222 , H01L23/5227
摘要： Integrated circuit (IC) chip "on-die" interconnection features (and methods for their manufacture) may improve signal connections and transmission through a data signal communication channel from one chip, through semiconductor device packaging, and to another component, such as another chip. Such chip interconnection features may include (1) "last silicon metal level (LSML)" data signal "leadway (LDW) routing" traces isolated between LSLM isolation (e.g., power and/or ground) traces to: (2) add a length of the isolated data signal LDW traces to increase a total length of and tune data signal communication channels extending through a package between two communicating chips and (3) create switched buffer (SB) pairs of data signal channels that use the isolated data signal LDW traces to switch the locations of the pairs data signal circuitry and surface contacts for packaging connection bumps.
摘要翻译：集成电路（IC）芯片“片上”（on-die）互连特征（以及用于其制造的方法）可以改善通过数据信号通信信道从一个芯片经过半导体器件封装到另一个组件（例如另一个芯片）的信号连接和传输。这样的芯片互连特征可以包括（1）“最后硅金属层（LSML）” 数据信号“引线（LDW）路由” （2）添加一段长度的隔离数据信号LDW迹线，以增加延伸通过两个通信芯片之间的封装的数据信号通信信道的总长度和调谐数据信号通信信道和（3）创建使用隔离数据信号LDW迹线的切换缓冲器（SB）对数据信号通道来切换数据信号电路和表面触点的位置以用于封装连接凸点。

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