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1. 发明申请

WO2010036676A3 INPUT/OUTPUT ARCHITECTURE FOR MOUNTED PROCESSORS, AND METHODS OF USING SAME 审中-公开
标题翻译：用于安装处理器的输入/输出结构，以及使用该结构的方法
公开(公告)号：WO2010036676A3
公开(公告)日：2010-07-22
申请号：PCT/US2009057968
申请日：2009-09-23
申请人： INTEL CORP , GANESAN SANKA , AYGUN KEMAL , RAMASWAMY CHANDRASHEKHAR , PALMER ERIC , BRAUNISCH HENNING
发明人： GANESAN SANKA , AYGUN KEMAL , RAMASWAMY CHANDRASHEKHAR , PALMER ERIC , BRAUNISCH HENNING
IPC分类号： H01L23/48 , H01L23/488
CPC分类号： H01L23/34 , H01L23/367 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L23/66 , H01L2223/6627 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00014 , H01L2924/15192 , H01L2924/19032 , H01L2224/0401
摘要： A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
摘要翻译：高速I / O走线是集成电路封装基板的I / O封装体系结构的一部分。集成电路封装衬底包括在管芯侧上的集成散热器覆盖区和I / O迹线，以与IC器件耦合以设置在IHS覆盖区内。 I / O走线包括一个位于IHS占位面积之外的引出端子，用于耦合IC设备以放置在IHS占用面积之外。高速I / O跟踪可以支持从每秒5千兆位（Gb / s）到40 Gb / s范围内的处理器的数据流速。

2. 发明申请

WO2009158098A2 PACKAGE ON PACKAGE USING A BUMP-LESS BUILD UP LAYER (BBUL) PACKAGE 审中-公开
标题翻译：包装使用无BUG-BUILD UP LAYER（BBUL）包装的包装
公开(公告)号：WO2009158098A2
公开(公告)日：2009-12-30
申请号：PCT/US2009/045231
申请日：2009-05-27
申请人： INTEL CORPORATION , PALMER, Eric, C. , GUZEK, John, S.
发明人： PALMER, Eric, C. , GUZEK, John, S.
IPC分类号： H01L23/12 , H01L23/48
CPC分类号： H01L23/3157 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L25/105 , H01L2224/16 , H01L2224/16235 , H01L2224/73204 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/01078 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15331 , H01L2924/18162 , H01L2924/00
摘要： In some embodiments, package on package using a bump-less build up layer (BBUL) package is presented. In this regard, an apparatus is introduced comprising a microelectronic die having an active surface, an inactive surface parallel to said active surface, and at least one side, an encapsulation material adjacent said at least one microelectronic die side, wherein said encapsulation material includes a bottom surface substantially planar to said microelectronic die active surface and a top surface substantially planar to said microelectronic die inactive surface, a through via connection in said encapsulation material extending from said top surface to said bottom surface, a first dielectric material layer disposed on at least a portion of said microelectronic die active surface and said encapsulation material surface, a plurality of build-up layers disposed on said first dielectric material layer, and a plurality of conductive traces disposed on said first dielectric material layer and said build-up layers and in electrical contact with said microelectronic die active surface. Other embodiments are also disclosed and claimed.
摘要翻译：在一些实施例中，提供了使用无凸起建立层（BBUL）封装的封装封装。在这方面，引入一种装置，其包括具有活性表面的微电子管芯，与所述有源表面平行的非活性表面，以及至少一个侧面，与所述至少一个微电子管芯侧相邻的封装材料，其中所述封装材料包括底表面与所述微电子管芯有效表面基本上平面，并且与所述微电子管芯非活性表面基本平面的顶表面，从所述顶表面延伸到所述底表面的所述封装材料中的通孔连接，至少设置在第一介电材料层所述微电子管芯有源表面和所述封装材料表面的一部分，设置在所述第一介电材料层上的多个堆积层，以及设置在所述第一介电材料层和所述堆积层上的多个导电迹线与所述微电子管芯有源表面电接触。还公开并要求保护其他实施例。

3. 发明申请

WO2010036676A2 INPUT/OUTPUT ARCHITECTURE FOR MOUNTED PROCESSORS, AND METHODS OF USING SAME 审中-公开
标题翻译：用于安装处理器的输入/输出结构，以及使用它们的方法
公开(公告)号：WO2010036676A2
公开(公告)日：2010-04-01
申请号：PCT/US2009/057968
申请日：2009-09-23
申请人： INTEL CORPORATION , GANESAN, Sanka , AYGUN, Kemal , RAMASWAMY, Chandrashekhar , PALMER, Eric , BRAUNISCH, Henning
发明人： GANESAN, Sanka , AYGUN, Kemal , RAMASWAMY, Chandrashekhar , PALMER, Eric , BRAUNISCH, Henning
IPC分类号： H01L23/48 , H01L23/488
CPC分类号： H01L23/34 , H01L23/367 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L23/66 , H01L2223/6627 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H01L2924/19032 , H01L2224/0401
摘要： A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
摘要翻译：高速I / O迹线是集成电路封装基板的I / O封装架构的一部分。集成电路封装衬底包括在芯片侧的集成的散热器占地面积，并且I / O迹线与要设置在IHS占地面积内的IC器件耦合。 I / O跟踪包括IHS封装之外的引脚输出端子，以连接到要设置在IHS占用空间之外的IC器件。高速I / O跟踪可以维持从5吉比特每秒（Gb / s）到40 Gb / s的处理器的数据流速。

4. 发明申请

WO2009158098A3 PACKAGE ON PACKAGE USING A BUMP-LESS BUILD UP LAYER (BBUL) PACKAGE 审中-公开
标题翻译：包装使用无BUG-BUILD UP LAYER（BBUL）包装的包装
公开(公告)号：WO2009158098A3
公开(公告)日：2010-02-25
申请号：PCT/US2009045231
申请日：2009-05-27
申请人： INTEL CORP , PALMER ERIC C , GUZEK JOHN S
发明人： PALMER ERIC C , GUZEK JOHN S
IPC分类号： H01L23/12 , H01L23/48
CPC分类号： H01L23/3157 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L25/105 , H01L2224/16 , H01L2224/16235 , H01L2224/73204 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/01078 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15331 , H01L2924/18162 , H01L2924/00
摘要： In some embodiments, package on package using a bump-less build up layer (BBUL) package is presented. In this regard, an apparatus is introduced comprising a microelectronic die having an active surface, an inactive surface parallel to said active surface, and at least one side, an encapsulation material adjacent said at least one microelectronic die side, wherein said encapsulation material includes a bottom surface substantially planar to said microelectronic die active surface and a top surface substantially planar to said microelectronic die inactive surface, a through via connection in said encapsulation material extending from said top surface to said bottom surface, a first dielectric material layer disposed on at least a portion of said microelectronic die active surface and said encapsulation material surface, a plurality of build-up layers disposed on said first dielectric material layer, and a plurality of conductive traces disposed on said first dielectric material layer and said build-up layers and in electrical contact with said microelectronic die active surface. Other embodiments are also disclosed and claimed.
摘要翻译：在一些实施例中，提供了使用无凸起建立层（BBUL）封装的封装封装。在这方面，引入一种装置，其包括具有活性表面的微电子管芯，与所述有源表面平行的非活性表面，以及至少一个侧面，与所述至少一个微电子管芯侧相邻的封装材料，其中所述封装材料包括底表面与所述微电子管芯有效表面基本上平面，并且与所述微电子管芯非活性表面基本平面的顶表面，从所述顶表面延伸到所述底表面的所述封装材料中的通孔连接，至少设置在第一介电材料层所述微电子管芯有源表面和所述封装材料表面的一部分，设置在所述第一介电材料层上的多个堆积层，以及设置在所述第一介电材料层和所述堆积层上的多个导电迹线与所述微电子管芯有源表面电接触。还公开并要求保护其他实施例。

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