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81. 发明授权

US09336860B1 Complementary bipolar SRAM 有权
标题翻译：互补双极型SRAM
公开(公告)号：US09336860B1
公开(公告)日：2016-05-10
申请号：US14717218
申请日：2015-05-20
申请人： International Business Machines Corporation
发明人： Tak H. Ning
IPC分类号： G11C11/00 , G11C11/411 , H01L27/11
CPC分类号： G11C11/416 , G11C11/411 , G11C11/4116 , H01L21/8228 , H01L21/8229 , H01L27/1025 , H01L27/11
摘要： A complementary lateral bipolar SRAM device. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state. In each said first and second set, a first bipolar transistor is an PNP type bipolar transistor, and a second bipolar transistor is an NPN type bipolar transistor, each said NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal. Emitter terminals of the PNP type transistors of each first and second inverter devices are electrically coupled together and receive a first applied wordline voltage. The first emitter terminals of each said NPN transistors of said first inverter and second inverter devices are electrically coupled together and receive a second applied voltage. 'The second emitter terminal of one NPN bipolar transistor of said first inverter is electrically coupled to a first bit line conductor, and the second emitter terminal of the NPN bipolar transistor of said second inverter device is electrically coupled to a second bit line.
摘要翻译：互补横向双极型SRAM器件。该器件包括：第一组和第二组横向双极晶体管，形成相应的第一反相器器件和第二反相器器件，第一和第二反相器器件交叉耦合以存储逻辑状态。在每个所述第一和第二组中，第一双极晶体管是PNP型双极晶体管，第二双极晶体管是NPN型双极晶体管，每个所述NPN型双极晶体管具有基极端子，第一发射极端子，第二发射极端子和集电极端子。每个第一和第二逆变器装置的PNP型晶体管的发射极端子电耦合在一起并接收第一施加的字线电压。所述第一反相器和第二反相器装置的每个所述NPN晶体管的第一发射极端子电耦合在一起并接收第二施加电压。 “所述第一反相器的一个NPN双极晶体管的第二发射极端子电耦合到第一位线导体，并且所述第二逆变器器件的NPN双极晶体管的第二发射极端子电耦合到第二位线。

82. 发明申请

US20150357338A1 METHODS AND STRUCTURES FOR MULTIPORT MEMORY DEVICES 有权
标题翻译：多个存储器件的方法和结构
公开(公告)号：US20150357338A1
公开(公告)日：2015-12-10
申请号：US14826522
申请日：2015-08-14
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： PERRY H. PELLEY , JAMES D. BURNETT
IPC分类号： H01L27/11 , H01L23/522 , H01L23/528 , H01L21/768
CPC分类号： H01L27/11 , G11C5/063 , G11C7/02 , G11C7/18 , G11C8/16 , G11C11/412 , H01L21/768 , H01L21/8228 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.
摘要翻译：存储器件包括使用衬底形成的存储单元，用于承载数据位的真位线BL0以及用于承载第一真位位线所携带的数据位的互补位线的互补位线。真正的位线耦合到存储单元并横向延伸到衬底上。真位线和互补位线彼此相邻并且垂直地堆叠在衬底上。

83. 发明授权

US09111786B1 Complementary field effect transistors using gallium polar and nitrogen polar III-nitride material 有权
标题翻译：使用镓极性和氮极性III族氮化物材料的互补场效应晶体管
公开(公告)号：US09111786B1
公开(公告)日：2015-08-18
申请号：US14578146
申请日：2014-12-19
申请人： Francis J. Kub , Travis J. Anderson , Michael A. Mastro , Charles R. Eddy, Jr. , Jennifer K. Hite
发明人： Francis J. Kub , Travis J. Anderson , Michael A. Mastro , Charles R. Eddy, Jr. , Jennifer K. Hite
IPC分类号： H01L29/778 , H01L27/092 , H01L27/095 , H01L29/20 , H01L29/201 , H01L29/205 , H01L29/04 , H01L29/36 , H01L29/78 , H01L29/66 , H01L21/335 , H01L21/8228 , H01L21/8238
CPC分类号： H01L27/095 , H01L21/02458 , H01L21/0254 , H01L21/02609 , H01L21/0262 , H01L21/02631 , H01L21/26546 , H01L21/28575 , H01L21/28587 , H01L21/30612 , H01L21/3065 , H01L21/762 , H01L21/8228 , H01L21/8238 , H01L21/8252 , H01L27/092 , H01L27/0921 , H01L27/0922 , H01L29/045 , H01L29/1075 , H01L29/1608 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/207 , H01L29/365 , H01L29/407 , H01L29/41725 , H01L29/41766 , H01L29/42364 , H01L29/452 , H01L29/51 , H01L29/66431 , H01L29/66439 , H01L29/66462 , H01L29/66477 , H01L29/778 , H01L29/7781 , H01L29/7782 , H01L29/7783 , H01L29/7784 , H01L29/7786 , H01L29/7787 , H01L29/78 , H01L29/7831
摘要： A device with N-Channel and P-Channel III-Nitride field effect transistors comprising a non-inverted P-channel III-Nitride field effect transistor on a first nitrogen-polar nitrogen face III-Nitride material, a non-inverted N-channel III-Nitride field effect transistor, epitaxially grown, a first III-Nitride barrier layer, two-dimensional hole gas, second III-Nitride barrier layer, and a two-dimensional hole gas. A method of making complementary non-inverted P-channel and non-inverted N-channel III-Nitride FET comprising growing epitaxial layers, depositing oxide, defining opening, growing epitaxially a first nitrogen-polar III-Nitride material, buffer, back barrier, channel, spacer, barrier, and cap layer, and carrier enhancement layer, depositing oxide, growing AlN nucleation layer/polarity inversion layer, growing gallium-polar III-Nitride, including epitaxial layers, depositing dielectric, fabricating P-channel III-Nitride FET, and fabricating N-channel III-Nitride FET.
摘要翻译：具有N沟道和P沟道III氮化物场效应晶体管的器件包括在第一氮极氮氮III氮化物材料上的非反相P沟道III-氮化物场效应晶体管，非反相N沟道 III-氮化物场效应晶体管，外延生长，第一III-氮化物阻挡层，二维空穴气体，第二III-氮化物阻挡层和二维空穴气体。制造互补的非反相P沟道和非反相N沟道III氮化物FET的方法，其包括生长外延层，沉积氧化物，限定开口，外延生长第一氮极III-氮化物材料，缓冲层，背部阻挡层，通道，间隔物，阻挡层和覆盖层，载流子增强层，沉积氧化物，生长AlN成核层/极性反转层，生长中的镓极性III-氮化物，包括外延层，沉积电介质，制造P沟道III-氮化物FET ，并制造N沟道III型氮化物FET。

84. 发明申请

US20150221647A1 Complementary Field Effect Transistors Using Gallium Polar and Nitrogen Polar III-Nitride Material 审中-公开
标题翻译：互补场效应晶体管使用镓极极和氮极三氮化物材料
公开(公告)号：US20150221647A1
公开(公告)日：2015-08-06
申请号：US14578146
申请日：2014-12-19
申请人： Francis J. Kub , Travis J. Anderson , Michael A. Mastro , Charles R. Eddy, JR. , Jennifer K. Hite
发明人： Francis J. Kub , Travis J. Anderson , Michael A. Mastro , Charles R. Eddy, JR. , Jennifer K. Hite
IPC分类号： H01L27/095 , H01L29/201 , H01L29/36 , H01L29/778 , H01L29/04 , H01L29/20 , H01L29/205
CPC分类号： H01L27/095 , H01L21/02458 , H01L21/0254 , H01L21/02609 , H01L21/0262 , H01L21/02631 , H01L21/26546 , H01L21/28575 , H01L21/28587 , H01L21/30612 , H01L21/3065 , H01L21/762 , H01L21/8228 , H01L21/8238 , H01L21/8252 , H01L27/092 , H01L27/0921 , H01L27/0922 , H01L29/045 , H01L29/1075 , H01L29/1608 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/207 , H01L29/365 , H01L29/407 , H01L29/41725 , H01L29/41766 , H01L29/42364 , H01L29/452 , H01L29/51 , H01L29/66431 , H01L29/66439 , H01L29/66462 , H01L29/66477 , H01L29/778 , H01L29/7781 , H01L29/7782 , H01L29/7783 , H01L29/7784 , H01L29/7786 , H01L29/7787 , H01L29/78 , H01L29/7831
摘要： A device with N-Channel and P-Channel III-Nitride field effect transistors comprising a non-inverted P-channel III-Nitride field effect transistor on a first nitrogen-polar nitrogen face III-Nitride material, a non-inverted N-channel III-Nitride field effect transistor, epitaxially grown, a first III-Nitride barrier layer, two-dimensional hole gas, second III-Nitride barrier layer, and a two-dimensional hole gas. A method of making complementary non-inverted P-channel and non-inverted N-channel III-Nitride FET comprising growing epitaxial layers, depositing oxide, defining opening, growing epitaxially a first nitrogen-polar III-Nitride material, buffer, back barrier, channel, spacer, barrier, and cap layer, and carrier enhancement layer, depositing oxide, growing AlN nucleation layer/polarity inversion layer, growing gallium-polar III-Nitride, including epitaxial layers, depositing dielectric, fabricating P-channel III-Nitride FET, and fabricating N-channel III-Nitride FET.
摘要翻译：具有N沟道和P沟道III氮化物场效应晶体管的器件包括在第一氮极氮氮III氮化物材料上的非反相P沟道III-氮化物场效应晶体管，非反相N沟道 III-氮化物场效应晶体管，外延生长，第一III-氮化物阻挡层，二维空穴气体，第二III-氮化物阻挡层和二维空穴气体。制造互补的非反相P沟道和非反相N沟道III氮化物FET的方法，其包括生长外延层，沉积氧化物，限定开口，外延生长第一氮极III-氮化物材料，缓冲层，背部阻挡层，通道，间隔物，阻挡层和覆盖层，载流子增强层，沉积氧化物，生长AlN成核层/极性反转层，生长中的镓极性III-氮化物，包括外延层，沉积电介质，制造P沟道III-氮化物FET ，并制造N沟道III型氮化物FET。

85. 发明授权

US08933490B2 Structure, method and system for complementary strain fill for integrated circuit chips 有权
标题翻译：用于集成电路芯片的互补应变填充的结构，方法和系统
公开(公告)号：US08933490B2
公开(公告)日：2015-01-13
申请号：US13774069
申请日：2013-02-22
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/118 , H01L27/12 , H01L21/8238 , G06F17/50 , H01L21/8234 , H01L27/02 , H01L27/088 , H01L27/092 , H01L21/8228 , H01L21/84
CPC分类号： G06F17/5072 , G06F17/5081 , H01L21/8228 , H01L21/823412 , H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L27/0922 , H01L27/1203
摘要： A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer.
摘要翻译：用于集成电路芯片的互补应变填充的结构，方法和系统。该结构包括具有多个n沟道和p沟道场效应晶体管（FET）的集成电路的第一区域; 第一区域的n沟道场效应晶体管（NFET）上的第一应力层，第一应力类型的第一应力层; 在第一区域的p沟道场效应晶体管（PFET）上的第二应力层，第二应力类型的第二应力层，与第一应力类型相反的第二应力类型; 和所述集成电路的第二区域，所述第二区域不包含FET，所述第二区域包含所述第一应力层的第一子区域和所述第二应力层的第二子区域。

86. 发明授权

US08853094B2 Method for manufacturing a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US08853094B2
公开(公告)日：2014-10-07
申请号：US13401537
申请日：2012-02-21
申请人： Thomas Scharnagl , Berthold Staufer
发明人： Thomas Scharnagl , Berthold Staufer
IPC分类号： H01L21/302 , H01L27/082 , H01L21/8228 , H01L29/66
CPC分类号： H01L29/66272 , H01L21/8228 , H01L27/082
摘要： A method for manufacturing a semiconductor structure comprising complementary bipolar transistors, wherein for manufacture of a PNP-type structure, an emitter layer having a surface oxide layer is present on top of an NPN-type structure, the emitter layer comprising lateral and vertical surfaces, and wherein for removal of the oxide layer, an ion etching step is applied, wherein for the on etching step a plasma for providing ions is generated in a vacuum chamber by RF coupling and the generated ions are accelerated by an acceleration voltage between the plasma and a wafer comprising the semiconductor structure, and wherein the plasma generation and the ion acceleration are controlled independently from each other.
摘要翻译：一种用于制造包括互补双极晶体管的半导体结构的方法，其中为了制造PNP型结构，具有表面氧化物层的发射极层位于NPN型结构的顶部，发射极层包括横向和垂直表面，并且其中为了去除氧化物层，应用离子蚀刻步骤，其中对于上蚀刻步骤，通过RF耦合在真空室中产生用于提供离子的等离子体，并且所产生的离子通过等离子体和包括半导体结构的晶片，并且其中等离子体产生和离子加速彼此独立地被控制。

87. 发明授权

US08581347B2 Forming bipolar transistor through fast EPI-growth on polysilicon 有权
标题翻译：通过在多晶硅上快速EPI生长形成双极晶体管
公开(公告)号：US08581347B2
公开(公告)日：2013-11-12
申请号：US12841275
申请日：2010-07-22
申请人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
发明人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
IPC分类号： H01L29/66
CPC分类号： H01L21/8249 , H01L21/8228 , H01L27/0623 , H01L27/0826
摘要： Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well.
摘要翻译：提供了一种半导体器件，其包括形成在同一衬底上的第一晶体管和第二晶体管。第一晶体管包括第一集电极，第一基极和第一发射极。第一集电器包括设置在衬底中的第一掺杂阱。第一基底包括设置在衬底上方和第一掺杂阱上方的第一掺杂层。第一发射器包括设置在第一掺杂层的一部分上的掺杂元件。第二晶体管包括第二集电极，第二基极和第二发射极。第二集电体包括衬底的掺杂部分。第二基底包括设置在衬底中并在衬底的掺杂部分上方的第二掺杂阱。第二发射器包括设置在衬底上方和第二掺杂阱上方的第二掺杂层。

88. 发明授权

US08531001B2 Complementary bipolar inverter 有权
标题翻译：互补双极型逆变器
公开(公告)号：US08531001B2
公开(公告)日：2013-09-10
申请号：US13158419
申请日：2011-06-12
申请人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L21/70
CPC分类号： H01L27/1203 , H01L21/8228 , H01L21/84 , H01L27/082
摘要： An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.
摘要翻译：示例性实施例是互补晶体管反相器电路。电路包括绝缘体上半导体（SOI）衬底，制造在SOI衬底上的横向PNP双极晶体管，以及制造在SOI衬底上的横向NPN双极晶体管。横向PNP双极晶体管包括PNP基极，PNP发射极和PNP集电极。横向NPN双极晶体管包括NPN基极，NPN发射极和NPN集电极。 PNP基极，PNP发射极，PNP集电极，NPN基极，NPN发射极和NPN集电极邻接SOI衬底的埋层绝缘体。

89. 发明申请

US20130161748A1 STRUCTURE, METHOD AND SYSTEM FOR COMPLEMENTARY STRAIN FILL FOR INTEGRATED CIRCUIT CHIPS 有权
公开(公告)号：US20130161748A1
公开(公告)日：2013-06-27
申请号：US13774069
申请日：2013-02-22
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/12 , G06F17/50
CPC分类号： G06F17/5072 , G06F17/5081 , H01L21/8228 , H01L21/823412 , H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L27/0922 , H01L27/1203
摘要： A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer.

90. 发明申请

US20130157433A1 METHODS FOR FORMING ELECTROSTATIC DISCHARGE PROTECTION CLAMPS WITH INCREASED CURRENT CAPABILITIES 有权
标题翻译：形成具有增加的电流能力的静电放电保护夹的方法
公开(公告)号：US20130157433A1
公开(公告)日：2013-06-20
申请号：US13770548
申请日：2013-02-19
申请人： Rouying Zhan , Amaury Gendron , Chai Ean Gill
发明人： Rouying Zhan , Amaury Gendron , Chai Ean Gill
IPC分类号： H01L29/66
CPC分类号： H01L21/8228 , H01L27/0259 , H01L29/66234
摘要： Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1
摘要翻译：提供了形成静电放电保护（ESD）夹具的方法。在一个实施例中，该方法包括形成至少一个具有延伸到衬底中的第一导电类型的第一阱区的晶体管。至少一个晶体管形成有具有第二相反导电类型的另一阱区，其延伸到衬底中以部分地形成集电极。晶体管阱区的横向边缘被隔开距离D，距离D至少部分地确定ESD钳位的阈值电压Vt1。第一导电类型的基极接触形成在第一阱区中，并且与第二导电类型的发射极分开横向距离Lbe。选择第一掺杂密度和横向距离Lbe以在1

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