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81. 发明授权

US06452265B1 Multi-chip module utilizing a nonconductive material surrounding the chips that has a similar coefficient of thermal expansion 失效
标题翻译：利用具有相似热膨胀系数的芯片周围的非导电材料的多芯片模块
公开(公告)号：US06452265B1
公开(公告)日：2002-09-17
申请号：US09493929
申请日：2000-01-28
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Rosemary A. Previti-Kelly , Edmund Sprogis
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Rosemary A. Previti-Kelly , Edmund Sprogis
IPC分类号： H01L2334
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3738 , H01L23/5389 , H01L24/96 , H01L24/97 , H01L2224/12105 , H01L2224/73204 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/0401
摘要： A multi-chip module is constructed by aligning prewired chips on a support wafer and depositing a nonconductive thermally conductive and electrically nonconductive material having a coefficient of thermal expansion that approximate that of the chips (e.g. silicon, silicon carbide, silicon germanium, germanium or SiCGe) to surround chips. After removal of the support wafer, processing of multi-chip module is finished with wiring on a shared surface of multi-chip module and chip surface.
摘要翻译：通过使支撑晶片上的预接线芯片对准并沉积具有接近芯片（例如硅，碳化硅，硅锗，锗或SiCGe）的热膨胀系数的非导电导热和非导电材料来构造多芯片模块）围绕芯片。拆卸支撑晶片后，多芯片模块的处理通过多芯片模块和芯片表面的共享表面上的布线完成。

82. 发明授权

US06344416B1 Deliberate semiconductor film variation to compensate for radial processing differences, determine optimal device characteristics, or produce small productions 失效
标题翻译：有意识的半导体薄膜变化来补偿径向处理差异，确定最佳的器件特性，或产生小的生产
公开(公告)号：US06344416B1
公开(公告)日：2002-02-05
申请号：US09523480
申请日：2000-03-10
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak
IPC分类号： H01L21311
CPC分类号： H01L22/20 , C23C16/04 , C23C16/513 , C23C16/52 , H01L21/31053 , H01L21/31116 , H01L21/32137 , H01L21/76229 , H01L21/8234 , Y10S438/911
摘要： Methods and apparatuses are disclosed that can introduce deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, to determine optimal device characteristics, or produce small production runs. The present invention radially varies the thickness and/or composition of a semiconductor film to compensate for a known radial variation in the semiconductor film that is caused by performing a subsequent semiconductor processing step on the semiconductor film. Additionally, methods and apparatuses are disclosed that can introduce deliberate semiconductor film variations to determine optimal device characteristics or produce small production runs. Introducing semiconductor film variations, such as thickness variations and/or composition variations, allow different devices to be made. A number of devices may be made having variations in semiconductor film. Because the semiconductor film has variations between the devices, device characteristics of the devices should be different. By measuring the device characteristics of devices having the variations, the device with the optimum device characteristic may be chosen, thereby indicating the appropriate semiconductor film thickness and/or composition. Moreover, small production runs of the same devices, having different characteristics, will allow the end user to select the appropriate devices for their needs.
摘要翻译：公开了可以在半导体制造期间引入有意的半导体膜变化以补偿径向处理差异，确定最佳器件特性或产生小的生产运行的方法和装置。本发明径向地改变半导体膜的厚度和/或组成，以补偿半导体膜中已知的半导体膜的径向变化，这是通过在半导体膜上进行随后的半导体处理步骤引起的。另外，公开了可以引入有意识的半导体薄膜变化以确定最佳的器件特性或产生小的生产运行。引入半导体薄膜变化，例如厚度变化和/或组成变化，允许制造不同的装置。可以制造多个器件，其具有半导体膜的变化。因为半导体薄膜在器件之间有变化，所以器件的器件特性应该是不同的。通过测量具有变化的器件的器件特性，可以选择具有最佳器件特性的器件，从而指示适当的半导体膜厚度和/或组成。此外，相同设备的小生产运行具有不同的特性，将允许最终用户根据需要选择适当的设备。

83. 发明授权

US06333229B1 Method for manufacturing a field effect transitor (FET) having mis-aligned-gate structure 失效
标题翻译：制造具有不对准栅极结构的场效应晶体管（FET）的方法
公开(公告)号：US06333229B1
公开(公告)日：2001-12-25
申请号：US09523839
申请日：2000-03-13
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak
IPC分类号： H01L21336
CPC分类号： H01L29/66621 , H01L21/28044 , H01L21/28114 , H01L29/42376 , H01L29/4925 , H01L29/7834
摘要： A viable T-gate FET is produced even when the cap of the “T” is mis-aligned from the stem of the “T”. A subtractive etch is used to selectively etch the material forming the cap of the T-gate and the material forming the stem of the T-gate in order to avoid the etching away of portions of the stem if the cap is mis-aligned relative to the stem. To that end, germanium (Ge) may be used as the material for the cap of the T-gate and poly silicon (polySi) may be used as the material for the stem of the T-gate. Since germanium can be etched selectively relative to silicon from 10:1 to as much as 20:1, the cap of the T can be formed without appreciable damage to the stem portion and thus without damage to the resultant FET device.
摘要翻译：即使当“T”的盖与“T”的杆不对齐时，也会产生可行的T型栅极FET。使用减法蚀刻来选择性地蚀刻形成T形栅的帽和形成T形栅的杆的材料的材料，以避免如果帽相对于茎。为此，可以使用锗（Ge）作为T型栅极的盖的材料，并且可以使用多晶硅（polySi）作为T型栅极的材料。由于锗可以相对于硅选择性地从10:1蚀刻到多达20:1，所以可以形成T的帽，而不会对柄部产生明显的损害，从而不会损坏所得到的FET器件。

84. 发明授权

US6150256A Method for forming self-aligned features 失效
标题翻译：形成自对准特征的方法
公开(公告)号：US6150256A
公开(公告)日：2000-11-21
申请号：US183338
申请日：1998-10-30
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： H01L21/027 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76825 , H01L21/0274 , H01L21/76802 , H01L21/76805 , H01L21/76811
摘要： The present invention provides for an improved method of creating vias and trenches during microchip fabrication. According to the invention, the vias and trenches are self-aligned during the photolithography process by using two layers of specially selected resists and exposing the resists such that the lower resist is exposed only where an opening has been formed in the upper resist layer. This self-aligning enables the vias to be printed as elongated shapes, which allows for the use of particularly effective image enhancement techniques. The invention further provides a simplified procedure for creating vias and trenches, in that only one etch step is required to simultaneously create both vias and trenches. An alternative embodiment of the invention allows looped or linked images, such as those printed using image enhancement techniques, to be trimmed to form isolated features.
摘要翻译：本发明提供了一种在微芯片制造期间产生通孔和沟槽的改进方法。根据本发明，通过使用两层特别选择的抗蚀剂，在光刻工艺期间，通孔和沟槽是自对准的，并且使抗蚀剂曝光，使得下抗蚀剂仅在上抗蚀剂层中形成开口的地方露出。这种自对准使通孔能够被印制成细长的形状，这允许使用特别有效的图像增强技术。本发明还提供了一种用于产生通孔和沟槽的简化过程，因为仅需要一个蚀刻步骤来同时产生通孔和沟槽。本发明的替代实施例允许将被修剪以形成隔离特征的循环或链接的图像，诸如使用图像增强技术印刷的图像。

85. 发明授权

US6007968A Method for forming features using frequency doubling hybrid resist and device formed thereby 失效
标题翻译：使用倍频混合抗蚀剂形成特征的方法和由此形成的器件
公开(公告)号：US6007968A
公开(公告)日：1999-12-28
申请号：US959779
申请日：1997-10-29
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： G03F1/00 , G03F7/038 , G03F7/20 , H01L21/027 , H01L21/02 , G03C5/00
CPC分类号： G03F7/70466 , G03F7/038 , H01L21/0274 , G03F7/2022
摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art by providing a method to form unlinked features using hybrid resist. The method uses a trim process in order to trim the linking features from the "loops" formed by the hybrid resist. This allows the method to form a plurality of unlinked features rather than the loops. In order to trim the ends, a relatively larger trim area is formed adjacent the narrow feature line, either by a second exposure step or by utilizing a grey scale reticle. The broader or wider open area allows features to be formed in the narrow feature lines and being trimmed from the relatively large areas, thereby resulting in district features rather than loops.
摘要翻译：本发明的优选实施例通过提供使用混合抗蚀剂形成不连接特征的方法来克服现有技术的局限性。该方法使用修剪工艺来修剪由混合抗蚀剂形成的“环”的连接特征。这允许该方法形成多个未链接的特征而不是循环。为了修剪端部，通过第二曝光步骤或通过利用灰度光罩，形成与窄特征线相邻的相对较大的修整区域。更宽或更宽的开放区域允许在窄特征线中形成特征并且从相对较大的区域修剪特征，从而导致区域特征而不是环。

86. 发明授权

US5998835A High performance MOSFET device with raised source and drain 失效
标题翻译：高性能MOSFET器件，具有升高的源极和漏极
公开(公告)号：US5998835A
公开(公告)日：1999-12-07
申请号：US24840
申请日：1998-02-17
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma , Jack A. Mandelman
IPC分类号： H01L21/225 , H01L21/336 , H01L29/78 , H01L29/50
CPC分类号： H01L29/66613 , H01L29/66621 , H01L29/7834 , H01L21/2255
摘要： A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are formed adjacent to opposite sides of the trench. Each diffusion layer is connected to the edge of the device channel by extending the diffusion layer along the side wall of the trench and under a portion of the trench.
摘要翻译：一种MOSFET器件及其制造方法。该器件具有形成在硅衬底中的沟槽。设备的通道位于沟槽的底部。扩散层邻近沟槽的相对侧形成。通过沿着沟槽的侧壁和沟槽的一部分延伸扩散层，将每个扩散层连接到器件沟道的边缘。

87. 发明授权

US08568604B2 CMOS gate structures fabricated by selective oxidation 有权
标题翻译：通过选择性氧化制造的CMOS栅极结构
公开(公告)号：US08568604B2
公开(公告)日：2013-10-29
申请号：US12186075
申请日：2008-08-05
申请人： Bruce B. Doris , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Bruce B. Doris , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： B44C1/22 , H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/823828 , H01L21/823864
摘要： A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial material that is deposited over a structure layer and covered by a cover layer. The sacrificial material layer and the cover layer are patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the material layer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.
摘要翻译：用于形成亚光刻结构的侧壁图像转印工艺采用沉积在结构层上并被覆盖层覆盖的牺牲材料层。牺牲材料层和覆盖层用常规抗蚀剂图案化并蚀刻以形成牺牲芯棒。心轴的边缘在低温下在等离子体中被氧化或氮化，之后剥离材料层和覆盖层，留下亚光刻的侧壁。侧壁用作硬掩模来蚀刻栅极导体层中的亚光刻栅极结构。

88. 发明申请

US20090014767A1 CARBON NANOTUBE CONDUCTOR FOR TRENCH CAPACITORS 有权
标题翻译：用于TRENCH电容器的碳纳米管导体
公开(公告)号：US20090014767A1
公开(公告)日：2009-01-15
申请号：US10596022
申请日：2003-12-18
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Larry A. Nesbit
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Larry A. Nesbit
IPC分类号： H01L27/108
CPC分类号： H01L27/10864 , B82Y10/00 , H01L27/10861 , Y10S977/936 , Y10S977/943 , Y10S977/948
摘要： A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.
摘要翻译：沟槽式存储装置包括在衬底（100）中的沟槽，具有衬在沟槽上的碳纳米管（202）的束和填充沟槽的沟槽导体（300）。可以在碳纳米管和沟槽的侧壁之间形成沟槽电介质（200）。碳纳米管束形成在沟槽内衬的开放圆筒结构。该器件通过在衬底上提供碳纳米管催化剂结构并对衬底中的沟槽进行图案化而形成; 然后将碳纳米管向下生长到沟槽中以与碳纳米管束对准沟槽，然后用沟槽导体填充沟槽。

89. 发明授权

US07385673B2 Immersion lithography with equalized pressure on at least projection optics component and wafer 有权
标题翻译：至少在投影光学部件和晶片上具有均衡压力的浸没光刻
公开(公告)号：US07385673B2
公开(公告)日：2008-06-10
申请号：US11160156
申请日：2005-06-10
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Peter H. Mitchell
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Peter H. Mitchell
IPC分类号： G03B27/42
CPC分类号： G03F7/70341
摘要： An immersion lithography apparatus and method, and a lithographic optical column structure are disclosed for conducting immersion lithography with at least the projection optics of the optical system and the wafer in different fluids at the same pressure. In particular, an immersion lithography apparatus is provided in which a supercritical fluid is introduced about the wafer, and another fluid, e.g., an inert gas, is introduced to at least the projection optics of the optical system at the same pressure to alleviate the need for a special lens. In addition, the invention includes an immersion lithography apparatus including a chamber filled with a supercritical immersion fluid and enclosing a wafer to be exposed and at least a projection optic component of the optical system.
摘要翻译：公开了一种浸没式光刻设备和方法以及平版印刷光学柱结构，用于在相同压力下用不同流体中的光学系统和晶片的至少投影光学器件进行浸没光刻。特别地，提供了一种浸没式光刻设备，其中超临界流体被引入晶片周围，并且另一种流体（例如惰性气体）在相同的压力下被引入光学系统的至少投影光学器件以减轻需要用于特殊镜头。此外，本发明包括浸没式光刻设备，其包括填充有超临界浸没流体的腔室并且封装要暴露的晶片和至少光学系统的投影光学部件。

90. 发明申请

US20080128811A1 SEMICONDUCTOR DEVICES WITH BURIED ISOLATION REGIONS 审中-公开
标题翻译：带有分离隔离区的半导体器件
公开(公告)号：US20080128811A1
公开(公告)日：2008-06-05
申请号：US12018886
申请日：2008-01-24
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger
IPC分类号： H01L29/786
CPC分类号： H01L29/0653 , B82Y10/00 , H01L21/28114 , H01L21/3086 , H01L21/31144 , H01L21/76224 , H01L21/76243 , H01L21/76267 , H01L21/76283 , H01L29/0649 , H01L29/0657 , H01L29/1083 , H01L29/165 , H01L29/66545 , H01L29/66575 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78654 , H01L29/78684
摘要： Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask and performing additional semiconductor processing steps using the nano-structures generated.
摘要翻译：半导体结构和形成半导体结构的方法。包括纳米结构或使用纳米结构制造的半导体结构。形成半导体结构的方法包括使用纳米掩模生成纳米结构，并使用所生成的纳米结构进行附加的半导体加工步骤。

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