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81. 发明授权

US07298648B2 Page buffer and multi-state nonvolatile memory device including the same 有权
标题翻译：页面缓冲器和包括其的多状态非易失性存储器件
公开(公告)号：US07298648B2
公开(公告)日：2007-11-20
申请号：US11228194
申请日：2005-09-19
申请人： Sung-Soo Lee , Young-Ho Lim , Hyun-Chul Cho , Dong-Hyuk Chae
发明人： Sung-Soo Lee , Young-Ho Lim , Hyun-Chul Cho , Dong-Hyuk Chae
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C2211/5642
摘要： According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line. The memory device is operable in a read mode which reads the threshold voltage state of the non-volatile memory cells and a programming mode which programs the threshold voltage state of the non-volatile memory cells, wherein the page buffer circuit is selectively responsive to the sub-latch data to inhibit flipping of the logic value of the main latch data in the programming mode.
摘要翻译：根据一个方面，存储单元阵列包括连接到多个非易失性存储单元的位线，其中非易失性存储单元可选择性地以至少第一，第二，第三和第四阈值电压状态中的任何一个编程，并且其中第一，第二，第三和第四阈值电压状态对应于由第一和第二位定义的四个不同的数据值。页面缓冲电路将逻辑值存储为主锁存数据，并且响应于主锁存信号，以根据位线的电压电平选择性地翻转主锁存数据的逻辑值。子锁存电路将逻辑值存储为子锁存数据，并且响应于子锁存信号，以根据位线的电压电平选择性地翻转子锁存数据的逻辑值。存储器件可读取读取非易失性存储器单元的阈值电压状态的读取模式和编程非易失性存储器单元的阈值电压状态的编程模式，其中页面缓冲器电路有选择地响应于子锁存数据，以禁止在编程模式下翻转主锁存器数据的逻辑值。

82. 发明授权

US07257028B2 Temperature compensated bit-line precharge 有权
标题翻译：温度补偿位线预充电
公开(公告)号：US07257028B2
公开(公告)日：2007-08-14
申请号：US10884152
申请日：2004-07-01
申请人： Kyeong-Han Lee , Sung-Soo Lee
发明人： Kyeong-Han Lee , Sung-Soo Lee
IPC分类号： G11C16/04 , G11C7/00
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/26
摘要： A nonvolatile semiconductor memory device compensates for temperature changes by holding constant a bit line precharge level. A memory device according to the present invention may include an electrically programmable memory cell array connected to a plurality of word lines and a plurality of bit lines, a bit line voltage supplying circuit for supplying a bit line voltage to the bit lines, a shut-off circuit connecting the memory cell array and the bit line voltage supplying circuit, and a shut-off controlling circuit for controlling the shut off circuit. The shut-off controlling circuit may be constructed to compensate for temperature changes in order to hold the bit-line precharge level constant.
摘要翻译：非易失性半导体存储器件通过保持恒定的位线预充电电平来补偿温度变化。根据本发明的存储器件可以包括连接到多个字线和多个位线的电可编程存储单元阵列，用于向位线提供位线电压的位线电压提供电路，连接存储单元阵列和位线电压供给电路的断开电路以及用于控制截止电路的切断控制电路。关断控制电路可以被构造为补偿温度变化，以便保持位线预充电电平恒定。

83. 发明授权

US07151702B2 High voltage generators having an integrated discharge path for use in non-volatile semiconductor memory devices 有权
标题翻译：具有用于非易失性半导体存储器件的集成放电路径的高压发生器
公开(公告)号：US07151702B2
公开(公告)日：2006-12-19
申请号：US10915294
申请日：2004-08-10
申请人： Wook-Ghee Han , Dae-Seok Byeon , Sung-Soo Lee , Young-Ho Lim
发明人： Wook-Ghee Han , Dae-Seok Byeon , Sung-Soo Lee , Young-Ho Lim
IPC分类号： G11C5/14
CPC分类号： G11C16/12 , G11C5/145
摘要： High voltage generators include a charge pump and a ripple reduction circuit that includes an integrated discharge path. The ripple reduction circuit limits the voltage level from a charge pump when the charge pump is in a first operating mode and provides a discharge path that from the output terminal of the ripple reduction circuit to the output of the charge pump when the charge pump is in a second operating mode. Semiconductor memories incorporating such high voltage generators are also provided. Coupling circuits having an integrated discharge path are also provided.
摘要翻译：高压发生器包括电荷泵和包括集成放电路径的纹波降低电路。当电荷泵处于第一操作模式时，纹波降低电路限制来自电荷泵的电压电平，并且当电荷泵处于第一操作模式时提供从脉动降低电路的输出端子到电荷泵的输出的放电路径第二种操作模式。还提供了包括这种高电压发生器的半导体存储器。还提供具有集成放电路径的耦合电路。

84. 发明授权

US07110292B2 Programming circuits and methods for multimode non-volatile memory devices 有权
公开(公告)号：US07110292B2
公开(公告)日：2006-09-19
申请号：US11020517
申请日：2004-12-22
申请人： Wook-Ghee Hahn , Sung-Soo Lee , Dae-Seok Byeon
发明人： Wook-Ghee Hahn , Sung-Soo Lee , Dae-Seok Byeon
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C8/08 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/30 , G11C2211/5641
摘要： A non-volatile memory device includes non-volatile memory cells, a respective one of which is configured to store a single bit in a single bit mode, and to store more than one bit in a multi-bit mode. A single voltage divider is configured to generate at a least a first program voltage for the non-volatile memory cells in the single bit mode, and to generate at least a second program voltage that is different from the first program voltage, for the non-volatile memory cells in the multi-bit mode.

85. 发明申请

US20050036369A1 Temperature compensated bit-line precharge 有权
标题翻译：温度补偿位线预充电
公开(公告)号：US20050036369A1
公开(公告)日：2005-02-17
申请号：US10884152
申请日：2004-07-01
申请人： Kyeong-Han Lee , Sung-Soo Lee
发明人： Kyeong-Han Lee , Sung-Soo Lee
IPC分类号： G11C16/06 , G11C11/34 , G11C16/02 , G11C16/04 , G11C16/24 , G11C16/26
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/26
摘要： A nonvolatile semiconductor memory device compensates for temperature changes by holding constant a bit line precharge level. A memory device according to the present invention may include an electrically programmable memory cell array connected to a plurality of word lines and a plurality of bit lines, a bit line voltage supplying circuit for supplying a bit line voltage to the bit lines, a shut-off circuit connecting the memory cell array and the bit line voltage supplying circuit, and a shut-off controlling circuit for controlling the shut off circuit. The shut-off controlling circuit may be constructed to compensate for temperature changes in order to hold the bit-line precharge level constant.
摘要翻译：非易失性半导体存储器件通过保持恒定的位线预充电电平来补偿温度变化。根据本发明的存储器件可以包括连接到多个字线和多个位线的电可编程存储单元阵列，用于向位线提供位线电压的位线电压提供电路，连接存储单元阵列和位线电压供给电路的断开电路以及用于控制截止电路的切断控制电路。关断控制电路可以被构造为补偿温度变化，以便保持位线预充电电平恒定。

86. 发明授权

US06826082B2 Programmable memory devices with latching buffer circuit and methods for operating the same 失效
标题翻译：具有锁存缓冲电路的可编程存储器件及其操作方法
公开(公告)号：US06826082B2
公开(公告)日：2004-11-30
申请号：US10403739
申请日：2003-03-31
申请人： Sang-Won Hwang , Sung-Soo Lee
发明人： Sang-Won Hwang , Sung-Soo Lee
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C7/065 , G11C16/24
摘要： Programmable memory devices include a memory cell having an associated bit line. A buffer circuit couples the bit line to a data line. The buffer circuit has a sense node coupled to the bit line and includes a latch circuit having a latch node coupled to the data line. A control circuit resets the latch node between a program operation of the memory cell and its corresponding program-verify operation. The memory devices may be NAND-type flash memory devices and the memory cell may be one of a string of memory cells connected in series between the bit line and a common source line. A transistor may couple the data line to the latch node and a transistor may couple the latch node to the sense node. Methods of operating the same are also provided.
摘要翻译：可编程存储器件包括具有相关位线的存储单元。缓冲电路将位线耦合到数据线。缓冲电路具有耦合到位线的感测节点，并且包括具有耦合到数据线的锁存节点的锁存电路。控制电路在存储器单元的编程操作与其对应的程序验证操作之间复位锁存节点。存储器件可以是NAND型闪存器件，并且存储器单元可以是在位线和公共源极线之间串联连接的一串存储器单元之一。晶体管可以将数据线耦合到锁存节点，并且晶体管可以将锁存器节点耦合到感测节点。还提供了其操作方法。

87. 发明授权

US06717861B2 Non-volatile semiconductor memory device capable of preventing program disturb due to noise voltage induced at a string select line and program method thereof 有权
标题翻译：能够防止由串选择线引起的噪声电压引起的程序干扰的非易失性半导体存储装置及其编程方法
公开(公告)号：US06717861B2
公开(公告)日：2004-04-06
申请号：US10006196
申请日：2001-12-04
申请人： Jae-Yong Jeong , Sung-Soo Lee
发明人： Jae-Yong Jeong , Sung-Soo Lee
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： Disclosed is a non-volatile semiconductor memory device including a circuit for controlling potentials of select lines and word lines in accordance with bit line setup, string select line setup, program and discharge periods of a program cycle. The control circuit biases a string select line to a power supply voltage during the bit line setup period in the program cycle, and to a voltage between the power supply voltage and ground voltage during the string select line setup and the program periods. According to the string select line control scheme, program disturb due to a noise voltage induced at a string select line when a program voltage is applied to a word line adjacent to the string select line is prevented.
摘要翻译：公开了一种非易失性半导体存储器件，其包括根据位线设置，串选择线设置，编程周期的编程和放电周期来控制选择线和字线的电位的电路。控制电路在编程周期中的位线建立期间将串选择线偏置为电源电压，并且在串选择线设置和程序周期期间将电源电压和接地电压之间的电压偏置。根据串选择线控制方案，防止当将编程电压施加到与串选择线相邻的字线时在串选择线处感应到的噪声电压时的程序干扰。

88. 发明授权

US06614688B2 Method of programming non-volatile semiconductor memory device 有权
公开(公告)号：US06614688B2
公开(公告)日：2003-09-02
申请号：US09990191
申请日：2001-11-20
申请人： Jae-Yong Jeong , Jin-Seon Yeom , Sung-Soo Lee
发明人： Jae-Yong Jeong , Jin-Seon Yeom , Sung-Soo Lee
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0483
摘要： A method of programming a non-volatile semiconductor memory device is provided. The method includes a bitline setup step, a well bias setup step, a program step, and a discharge step. In the bitline setup step, either a ground or power supply voltage is supplied respectively to bitlines according to data bits stored in page buffers, and a pocket P-well area is biased with the ground voltage. In the well bias setup step, the ground voltage applied to the pocket P-well area is cut off to make the second well area attain a floating state. Under such a condition, the pocket P-well area is biased with a coupling voltage, which is lower than the ground voltage, through a coupling capacitance between the pocket P-well area and a common source line, or a coupling capacitance between the pocket P-well area and an N-well area. In the program step, a program voltage is supplied to selected wordlines and a pass voltage is supplied to unselected wordlines, with the floating second well area biased with the coupling voltage. Therefore, the pocket P-well area is biased with a negative voltage through the capacitance coupling.

89. 发明授权

US5548555A Method and circuit for repairing defect in a semiconductor memory device 失效
标题翻译：修复半导体存储器件缺陷的方法和电路
公开(公告)号：US5548555A
公开(公告)日：1996-08-20
申请号：US420835
申请日：1995-04-11
申请人： Sung-Soo Lee , Jin-Ki Kim
发明人： Sung-Soo Lee , Jin-Ki Kim
IPC分类号： G11C29/00 , G11C29/04 , G11C29/24 , G11C7/00
CPC分类号： G11C29/785 , G11C29/24
摘要： A method and a circuit for repairing defect by substituting a redundant memory cell for a defective memory cell in the semiconductor memory device. The circuit comprises charging nodes connected parallel to a number of electrical fuses; a device for outputting a storage signal of a defective address in response to an external control signal; a device for providing current to the charging node in response to the storage signal of the defective address; a redundant sense amplifier for outputting a redundant block driving signal to substitute a defective address in response to a logic level of the charging node; and a controller for decoding an address signal provided from the outside of the memory device so that a current path is formed in a selected fuse and the fuse is blew by current provided from the charging node, the controller being activated by the storage signal of the defective address.
摘要翻译：一种用于通过在半导体存储器件中替换有缺陷存储单元的冗余存储单元来修复缺陷的方法和电路。该电路包括与多个电保险丝并联连接的充电节点; 用于响应于外部控制信号输出缺陷地址的存储信号的装置; 用于响应于所述有缺陷地址的存储信号向所述计费节点提供电流的装置; 冗余感测放大器，用于响应于所述充电节点的逻辑电平输出冗余块驱动信号以代替缺陷地址; 以及控制器，用于对从存储器件的外部提供的地址信号进行解码，使得电流路径形成在所选择的熔丝中，并且熔丝被从充电节点提供的电流吹动，所述控制器由所述存储信号的存储信号激活有缺陷的地址。

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