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1. 发明专利

IL226043D0 Method for purifying human granulocyte-colony stimulating factor from recombinant e. coli 未知
公开(公告)号：IL226043D0
公开(公告)日：2013-06-27
申请号：IL22604313
申请日：2013-04-28
申请人： HANMI SCIENCE CO LTD , SUNG CHUL CHOI , JIN KI KIM , YOUNG HAK OH , JONG SOO LEE
IPC分类号： C07K20060101

2. 发明专利

IL226043A Method for purifying human granulocyte-colony stimulating factor from recombinant e. coli 未知
公开(公告)号：IL226043A
公开(公告)日：2017-03-30
申请号：IL22604313
申请日：2013-04-28
申请人： HANMI SCIENCE CO LTD , SUNG CHUL CHOI , JIN KI KIM , YOUNG HAK OH , JONG SOO LEE
发明人： SUNG CHUL CHOI , JIN KI KIM , YOUNG HAK OH , JONG SOO LEE

3. 发明授权

US09230654B2 Method and system for accessing a flash memory device 有权
公开(公告)号：US09230654B2
公开(公告)日：2016-01-05
申请号：US13790361
申请日：2013-03-08
申请人： Jin-Ki Kim , Hong Beom Pyeon
发明人： Jin-Ki Kim , Hong Beom Pyeon
IPC分类号： G11C16/00 , G11C16/06 , G06F13/42 , G11C5/06 , G11C7/10 , G11C8/10 , G11C16/10 , G11C16/26
CPC分类号： G06F3/0611 , G06F3/0655 , G06F3/0688 , G06F13/4243 , G11C5/066 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C8/10 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C2207/107 , G11C2216/30
摘要： An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

4. 发明授权

US09098430B2 Composite semiconductor memory device with error correction 有权
标题翻译：具有误差校正的复合半导体存储器件
公开(公告)号：US09098430B2
公开(公告)日：2015-08-04
申请号：US13038461
申请日：2011-03-02
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C29/00 , G06F11/10 , G11C29/04
CPC分类号： G06F11/1044 , G06F11/1048 , G11C2029/0411 , H03M13/05 , H03M13/611
摘要： A composite semiconductor memory device, comprising: a plurality of nonvolatile memory devices; and an interface device connected to the plurality of nonvolatile memory devices and for connection to a memory controller, the interface device comprising an error correction coding (ECC) engine. Also, a memory system, comprising: a memory controller; and at least one composite semiconductor memory device configured for being written to and read from by the memory controller and comprising a built-in error correction coding (ECC) engine. Also, a memory system, comprising: a composite semiconductor memory device comprising a plurality of nonvolatile memory devices; and a memory controller connected to the at least one composite semiconductor memory device, for issuing read and write commands to the composite semiconductor memory device to cause data to be written to or read from individual ones of the nonvolatile memory devices; the composite semiconductor memory device providing error-free writing and reading of the data.
摘要翻译：一种复合半导体存储器件，包括：多个非易失性存储器件; 以及连接到所述多个非易失性存储器件并且用于连接到存储器控制器的接口设备，所述接口设备包括纠错编码（ECC）引擎。另外，一种存储器系统，包括：存储器控制器; 以及至少一个复合半导体存储器件，被配置为被存储器控制器写入和读出，并且包括内置纠错编码（ECC）引擎。另外，一种存储系统，包括：复合半导体存储器件，其包括多个非易失性存储器件; 以及存储器控制器，连接到所述至少一个复合半导体存储器件，用于向所述复合半导体存储器件发出读取和写入命令，以使数据被写入或从所述非易失性存储器件中的各个写入; 所述复合半导体存储器件提供无错误的写入和读取数据。

5. 发明授权

US08984249B2 ID generation apparatus and method for serially interconnected devices 有权
标题翻译：用于串行互连设备的ID产生设备和方法
公开(公告)号：US08984249B2
公开(公告)日：2015-03-17
申请号：US11613563
申请日：2006-12-20
申请人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Steven Przybylski
发明人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Steven Przybylski
IPC分类号： G06F12/00 , G11C7/20 , G06F13/42 , G11C7/10 , G11C19/00 , G11C29/44
CPC分类号： G11C7/20 , G06F13/4291 , G11C7/10 , G11C7/1003 , G11C19/00 , G11C2029/4402
摘要： A plurality of memory devices (e.g., DRAMs, SRAMs, NAND Flash, NOR Flash) is serially interconnected. Each of the interconnected devices receives a device identifier (ID) and latches it as its ID. Each device includes a circuit for calculating another ID or an incremented ID to generate it. The generated ID is transferred to another device and the ID is incremented in each of the devices in the serial interconnection. The last device in the interconnection provides a last generated ID that is provided to a memory controller having a recognition circuit that recognizes the total number of the serially interconnected devices, from the provided last generated ID. The recognition circuit recognizes the total output latency of the devices in the serial interconnection.
摘要翻译：多个存储器件（例如，DRAM，SRAM，NAND闪存，NOR闪存）被串联连接。每个互连设备接收设备标识符（ID）并将其锁定为其ID。每个设备包括用于计算另一个ID或增加的ID以生成它的电路。生成的ID被传送到另一个设备，并且ID在串行互连中的每个设备中增加。互连中的最后一个设备提供最后生成的ID，其提供给具有从所提供的最后生成的ID识别串行互连设备的总数的识别电路的存储器控制器。识别电路识别串行互连中设备的总输出延迟。

6. 发明授权

US08903148B2 X-ray imaging apparatus and method of updating a pixel map 有权
标题翻译： X射线成像装置和更新像素图的方法
公开(公告)号：US08903148B2
公开(公告)日：2014-12-02
申请号：US13541820
申请日：2012-07-05
申请人： Ho Jun Lee , Jin Ki Kim
发明人： Ho Jun Lee , Jin Ki Kim
IPC分类号： G06K9/00 , G06T5/00
CPC分类号： G06T5/002 , G06T2207/10116 , G06T2207/30004 , Y10S128/922
摘要： An X-ray imaging apparatus and a method of updating a pixel map correct a bad pixel of an X-ray transmission image. An X-ray transmission image is generated by detecting an X-ray penetrating an object, and it is determined whether a difference between a value of each one of the pixels forming the X-ray transmission image and a value of a nearby pixel adjacent to the each one of the pixels is equal to or greater than a reference value. A pixel having a value representing a difference equal to or greater than the reference value is determined as a candidate for a bad pixel. A message is displayed which requests a selection of whether to determine if the candidate is a bad pixel. The pixel map is updated by reflecting the determined bad pixel on the pixel map.
摘要翻译： X射线成像装置和更新像素图的方法校正X射线透射图像的不良像素。通过检测穿透物体的X射线来生成X射线透射图像，并且确定形成X射线透射图像的每个像素的值和与其相邻的附近像素的值之间的差异像素中的每一个等于或大于参考值。具有表示等于或大于参考值的差的值的像素被确定为坏像素的候选。显示一个消息，其请求选择是否确定候选者是否是不良像素。通过在像素图上反映确定的不良像素来更新像素图。

7. 发明授权

US08866303B2 Semiconductor device with configurable through-silicon vias 有权
标题翻译：具有可配置的硅通孔的半导体器件
公开(公告)号：US08866303B2
公开(公告)日：2014-10-21
申请号：US13094613
申请日：2011-04-26
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： H01L33/00 , H01L25/065 , G11C5/02 , G11C29/00 , G11C8/12 , H01L23/48
CPC分类号： H01L25/0657 , G11C5/02 , G11C8/12 , G11C29/702 , H01L23/481 , H01L2224/16145 , H01L2225/06513 , H01L2225/06544
摘要： Disclosed is a semiconductor device that comprises a plurality of through-silicon vias (TSVs), a signal line and a selective connector for causing the signal line to be either electrically connected to one of the TSVs or electrically isolated from all of the TSVs, based on a control signal.
摘要翻译：公开了一种半导体器件，其包括多个穿硅通孔（TSV），信号线和选择性连接器，用于使信号线电连接到TSV之一或与所有TSV电隔离，基于控制信号。

8. 发明授权

US08843694B2 System and method of page buffer operation for memory devices 有权
标题翻译：存储器件的页面缓冲操作的系统和方法
公开(公告)号：US08843694B2
公开(公告)日：2014-09-23
申请号：US13302413
申请日：2011-11-22
申请人： Hong Beom Pyeon , Jin-Ki Kim , HakJune Oh
发明人： Hong Beom Pyeon , Jin-Ki Kim , HakJune Oh
IPC分类号： G06F13/00 , G06F13/28 , G11C7/10 , G06F12/08
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/1044 , G06F2212/2022 , G06F2212/3042 , G06F2212/7203 , G06F2212/7208 , G11C7/1039 , G11C7/106 , G11C7/1087 , G11C2207/2245
摘要： Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.
摘要翻译：提供了系统和方法，用于使用通过公共总线连接到存储器控制器的存储器件的页缓冲器。使用存储器件的页缓冲器作为写入存储器件的存储器单元的数据的临时缓存。这可以允许内存控制器使用内存设备作为临时缓存，以便内存控制器可以释放自己内存中的空间。

9. 发明授权

US08825939B2 Semiconductor memory device suitable for interconnection in a ring topology 有权
标题翻译：适用于环形拓扑互连的半导体存储器件
公开(公告)号：US08825939B2
公开(公告)日：2014-09-02
申请号：US12141384
申请日：2008-06-18
申请人： HakJune Oh , Jin-Ki Kim
发明人： HakJune Oh , Jin-Ki Kim
IPC分类号： G06F12/00 , G11C8/00
CPC分类号： G11C16/10 , G06F13/4239 , G11C7/10 , G11C7/1003
摘要： A semiconductor memory device, which comprises: memory; a plurality of inputs for receiving a command latch enable signal, an address latch enable signal, an information signal and a select signal indicative of whether the memory device has been selected by a controller; a plurality of outputs for releasing a set of output signals towards a next device; control circuitry; and bypass circuitry. When the select signal is indicative of the memory device having been selected by the controller, the control circuitry is configured to interpret the information signal based on the command latch enable signal and the address latch enable signal. When the select signal is indicative of the memory device not having been selected by the controller, the bypass circuitry is configured to transfer the command latch enable signal, the address latch enable signal and the information signal to the outputs of the memory device.
摘要翻译：一种半导体存储器件，包括：存储器; 用于接收命令锁存使能信号，地址锁存使能信号，信息信号和指示存储器件是否被控制器选择的选择信号的多个输入; 多个输出，用于向下一个装置释放一组输出信号; 控制电路; 和旁路电路。当选择信号指示由控制器选择的存储器件时，控制电路被配置为基于命令锁存使能信号和地址锁存使能信号来解释信息信号。当选择信号指示存储器件未被控制器选择时，旁路电路被配置为将命令锁存使能信号，地址锁存使能信号和信息信号传送到存储器件的输出。

10. 发明授权

US08819377B2 System and method of operating memory devices of mixed type 有权
标题翻译：操作混合型存储器件的系统和方法
公开(公告)号：US08819377B2
公开(公告)日：2014-08-26
申请号：US13038997
申请日：2011-03-02
申请人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
发明人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
IPC分类号： G06F12/00
CPC分类号： G06F13/4239 , G11C16/08 , G11C16/20 , G11C2216/30
摘要： A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.
摘要翻译：提供了存储器系统结构，其中存储器控制器控制串行互连配置中的存储器件。存储器控制器具有用于发送存储器命令的输出端口和用于接收用于请求这样的响应的那些存储器命令的存储器响应的输入端口。每个存储器件包括诸如NAND型闪存，NOR型闪速存储器，随机存取存储器和静态随机存取存储器之类的存储器。每个存储器命令特定于目标存储器件的存储器类型。存储器命令和存储器响应的数据路径由互连提供。给定的存储器命令遍历存储器件以达到其串行互连配置的预期存储器件。在其接收时，预期的存储器件执行给定的存储器命令，并且如果适当的话，向下一个存储器件发送存储器响应。存储器响应被传送到存储器控制器。

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