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81. 发明授权

US06912438B2 Using scatterometry to obtain measurements of in circuit structures 失效
标题翻译：使用散射法获得电路结构的测量
公开(公告)号：US06912438B2
公开(公告)日：2005-06-28
申请号：US10277016
申请日：2002-10-21
申请人： Bryan K. Choo , Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan
发明人： Bryan K. Choo , Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan
IPC分类号： G01N21/47 , H01L21/66 , G06F19/00
CPC分类号： H01L22/20 , G01N21/4738 , H01L2924/0002 , H01L2924/00
摘要： A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. Measurements are taken in accordance with scatterometry based techniques of repeating in circuit structures that evolve on a wafer as the wafer undergoes the fabrication process. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Additionally, the measurements can be employed in determining whether to discard the wafer or portions thereof based on a cost benefit analysis, for example. Directly measuring in circuit structures mitigates sacrificing valuable chip real estate as test grating structures may not need to be formed within the wafer, and also facilitates control over the elements that actually affect resulting chip performance.
摘要翻译：公开了用于监测和控制半导体制造工艺的系统和方法。根据基于散射法的技术进行测量，该技术在晶片经历制造过程时在晶片上发生的电路结构中重复。可以采用测量来产生可以用于选择性地调整一个或多个制造部件和/或与其相关联的操作参数以适应制造过程的前馈和/或反馈控制数据。另外，例如，可以基于成本效益分析来确定是否丢弃晶片或其部分的测量。在电路结构中的直接测量减轻了牺牲有价值的芯片的不动产，因为测试光栅结构可能不需要在晶片内形成，并且还有助于对实际影响芯片性能的元件的控制。

82. 发明授权

US06878560B1 Fab correlation system 有权
标题翻译： Fab相关系统
公开(公告)号：US06878560B1
公开(公告)日：2005-04-12
申请号：US10302091
申请日：2002-11-22
申请人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
发明人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , G05B2219/31457 , G05B2219/32191 , G05B2219/45031 , H01L2924/0002 , H01L2924/00
摘要： A system comprised of a plurality of fabs that are operatively coupled and share data from a common framework for correlating production. The fabs can be coupled via Internet, cellular, optical, landline, microwave and satellite communication means and the like. Data can be transferred to and/or received from a central, integrated correlating entity or from several distributed correlating entities. The fabs send and receive correlating data that relates to production information such as tolerances, critical dimensions, geometry and the like. The correlating entity(s) has the capability to increase production by performing probabilistic computations on the received correlating data and utilizing the resulting information to maintain correlating parameters at remote locations. The computations performed can include such calculations as Bayesian inferencing and the like. The system inherently precludes the necessity for physically transporting parametric test entities between different fab or tooling locations.
摘要翻译：由多个工厂组成的系统，其可操作地耦合并且共享来自公共框架的数据以用于生产。该晶圆厂可以通过互联网，蜂窝，光学，固定电话，微波和卫星通信装置等耦合。可以将数据传送到中央集成的相关实体或从多个分散的相关实体传送到和/或从中央集成的相关实体接收数据。制造厂发送和接收与生产信息相关的相关数据，例如公差，关键尺寸，几何形状等。相关实体具有通过对接收到的相关数据执行概率计算并利用所得到的信息来维持远程位置处的相关参数来增加产量的能力。执行的计算可以包括诸如贝叶斯推理等的计算。该系统固有地排除了在不同晶圆厂或模具位置之间物理传输参数测试实体的必要性。

83. 发明申请

US20050048741A1 Pattern recognition and metrology structure for an x-initiative layout design 失效
标题翻译：模式识别和计量结构，用于x-initiative布局设计
公开(公告)号：US20050048741A1
公开(公告)日：2005-03-03
申请号：US10653309
申请日：2003-09-02
申请人： Khoi Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： G03F7/20 , G03F9/00 , H01L21/301
CPC分类号： G03F7/70625 , G03F7/70633 , G03F9/7076 , Y10S438/975
摘要： The present invention relates to inspection methods and systems utilized to provide a best means for inspection of a wafer. The methods and systems include wafer-to-reticle alignment, layer-to-layer alignment and wafer surface feature inspection. The wafer-to-reticle alignment is improved by the addition of diagonal lines to existing alignment marks to decrease the intersection size and corresponding area that a desired point can reside. Layer-to-layer alignment is improved in a similar manner by the addition of oblique and/or non-linear line segments to existing overlay targets. Also, providing for wafer surface inspection in a multitude of desired diagonal axes allows for more accurate feature measurement.
摘要翻译：本发明涉及用于提供用于检查晶片的最佳方法的检查方法和系统。该方法和系统包括晶片到标线片对准，层间对准和晶片表面特征检查。通过将对角线添加到现有的对准标记来减小交叉点大小和期望点可以驻留的对应区域来改善晶片到标线阵列对准。通过向现有覆盖目标添加倾斜和/或非线性线段，以类似的方式改善了层间对齐。此外，在多个所需的对角轴中提供晶片表面检查允许更精确的特征测量。

84. 发明授权

US06790790B1 High modulus filler for low k materials 失效
标题翻译：用于低k材料的高模量填料
公开(公告)号：US06790790B1
公开(公告)日：2004-09-14
申请号：US10302227
申请日：2002-11-22
申请人： Christopher F. Lyons , Bharath Rangarajan
发明人： Christopher F. Lyons , Bharath Rangarajan
IPC分类号： H01L2131
CPC分类号： H01L21/31058 , H01L21/02118 , H01L21/0212
摘要： Disclosed are methods for processing a low k material involving providing a low k material layer comprising one or more low k polymer materials and one or more high modulus fillers on a semiconductor substrate, and chemical mechanical polishing the low k material layer so as to remove a portion of the low k material layer from the semiconductor substrate without substantially damaging unremoved portions of the low k material layer. In this connection, low k material layers for a semiconductor structure containing one or more low k polymer materials and one or more high modulus fillers are disclosed, as well as methods of making the low k material layers.
摘要翻译：公开了一种处理低k材料的方法，包括在半导体衬底上提供包含一种或多种低k聚合物材料和一种或多种高模量填料的低k材料层，以及化学机械抛光低k材料层，以除去来自半导体衬底的低k材料层的一部分，而不会基本上损坏低k材料层的未被除去的部分。在这方面，公开了用于包含一种或多种低k聚合物材料和一种或多种高模量填料的半导体结构的低k材料层，以及制备低k材料层的方法。

85. 发明授权

US06762133B1 System and method for control of hardmask etch to prevent pattern collapse of ultra-thin resists 失效
标题翻译：用于控制硬掩模蚀刻的系统和方法，以防止超薄抗蚀剂的图案崩溃
公开(公告)号：US06762133B1
公开(公告)日：2004-07-13
申请号：US09911241
申请日：2001-07-23
申请人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan
发明人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan
IPC分类号： H01L4302
CPC分类号： G03F7/40 , H01L21/0274 , H01L21/0337
摘要： The present invention relates to systems and methods for mitigating pattern collapse in ultra-thin resist processing. In one embodiment, the present invention relates to etching extremely fine patterns into a hardmask immediately after developing an ultra-thin resist, wherein the resist is not dried.
摘要翻译：本发明涉及减轻超薄抗蚀剂加工中的图案塌陷的系统和方法。在一个实施例中，本发明涉及在显影超薄抗蚀剂之后将极细图案刻蚀成硬掩模，其中抗蚀剂不被干燥。

86. 发明授权

US06746822B1 Use of surface coupling agent to improve adhesion 有权
标题翻译：使用表面偶联剂改善附着力
公开(公告)号：US06746822B1
公开(公告)日：2004-06-08
申请号：US10050484
申请日：2002-01-16
申请人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh
发明人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh
IPC分类号： G03F720
CPC分类号： G03F7/265 , H01L21/0273 , H01L21/31144 , H01L21/32139
摘要： Disclosed are methods of processing a semiconductor structure, involving the steps of depositing a light-degradable surface coupling agent on a semiconductor substrate; depositing a resist over the light-degradable surface coupling agent; irradiating portions of the resist, wherein the light-degradable surface coupling agent under the irradiated portions of the resist at least partially decomposes; and developing the resist.
摘要翻译：公开了处理半导体结构的方法，包括在半导体衬底上沉积可光降解的表面偶联剂的步骤; 在光可降解表面偶联剂上沉积抗蚀剂; 照射抗蚀剂的部分，其中抗蚀剂照射部分下的可光降解表面偶联剂至少部分分解; 并开发抗蚀剂。

87. 发明授权

US06741445B1 Method and system to monitor and control electro-static discharge 失效
标题翻译：监测和控制静电放电的方法和系统
公开(公告)号：US06741445B1
公开(公告)日：2004-05-25
申请号：US10050458
申请日：2002-01-16
申请人： Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
发明人： Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： H01T2300
CPC分类号： H01L21/67253
摘要： A system and methodology is provided for monitoring and controlling static charge during wafer and mask fabrication. The static charge on a target device is monitored. If the static charge becomes too high, corrective actions are taken to reduce the static charge. An antistatic solution is dispensed on the target device. The system and methodology provided reduce damage resulting from electrostatic discharge during fabrication. The system and methodology also reduce delays during fabrication by automatically controlling static charge without the need for manual intervention.
摘要翻译：提供了一种用于在晶片和掩模制造期间监测和控制静电荷的系统和方法。监视目标设备上的静电荷。如果静电荷过高，则采取纠正措施减少静电。抗静电溶液分配在目标装置上。所提供的系统和方法减少了制造过程中静电放电造成的损坏。该系统和方法还通过自动控制静电而减少制造过程中的延迟，而无需人工干预。

88. 发明授权

US06724476B1 Low defect metrology approach on clean track using integrated metrology 失效
标题翻译：使用综合计量的清洁轨道的低缺陷计量方法
公开(公告)号：US06724476B1
公开(公告)日：2004-04-20
申请号：US10261756
申请日：2002-10-01
申请人： Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
发明人： Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
IPC分类号： G01N2100
CPC分类号： G01N21/9501
摘要： One aspect of the present invention relates to a system and method of monitoring for defects on a wafer before and after forming a photoresist layer on the wafer. The system includes a device fabrication system comprising one or more wafer processing system components for producing a device; a defect metrology system integrated within and on track with the fabrication system operative to inspect the wafer for defects before it proceeds to photoresist processing; and a wafer cleaning system for reducing an amount of defects detected on the front and/or back side of the wafer. If the amount of defects have been sufficiently reduced, the front side of the wafer may be coated with a photoresist. Subsequently, the back side of the wafer may be inspected and cleaned while protecting the front side from damage. Cleaning of the wafer may be performed with a thermal shock treatment, for example.
摘要翻译：本发明的一个方面涉及在晶片上形成光致抗蚀剂层之前和之后对晶片上的缺陷进行监测的系统和方法。该系统包括装置制造系统，其包括用于产生装置的一个或多个晶片处理系统部件; 在制造系统内部和轨道上集成的缺陷计量系统，其操作用于在进行光致抗蚀剂处理之前检查晶片的缺陷; 以及用于减少在晶片的前侧和/或后侧检测到的缺陷量的晶片清洁系统。如果缺陷的量已经被充分降低，则晶片的前侧可以涂覆有光致抗蚀剂。随后，可以在保护前侧免受损伤的同时检查和清洁晶片的背面。例如，可以进行热冲击处理来进行晶片的清洁。

89. 发明授权

US06702648B1 Use of scatterometry/reflectometry to measure thin film delamination during CMP 有权
标题翻译：在CMP期间使用散射/反射测量薄膜分层
公开(公告)号：US06702648B1
公开(公告)日：2004-03-09
申请号：US10277559
申请日：2002-10-22
申请人： Steven C. Avanzino , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
发明人： Steven C. Avanzino , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： B24B4900
CPC分类号： B24B37/013 , B24B49/12
摘要： One aspect of the present invention relates to a system and method for examining a wafer for delamination in real time while polishing the wafer. The system comprises a polishing system programmed to planarize one or more film layers formed on at least a portion of a semiconductor wafer surface; a real-time metrology system coupled to the polishing system such that the metrology system examines the layers as they are planarized; and one or more delamination sensors, wherein at least a portion of each sensor is integrated into the polishing system in order to provide data to the metrology system and wherein the sensor comprises at least one optical element to detect delamination during polishing. The method involves polishing at least a portion of an uppermost film layer and examining at least a portion of a layer underlying the uppermost film layer for delamination as the uppermost layer is being polished.
摘要翻译：本发明的一个方面涉及一种用于在抛光晶片的同时检查晶片以实时分层的系统和方法。该系统包括被编程为平坦化形成在半导体晶片表面的至少一部分上的一个或多个膜层的抛光系统; 耦合到抛光系统的实时计量系统，使得计量系统在平面化时对层进行检查; 和一个或多个分层传感器，其中每个传感器的至少一部分被集成到抛光系统中，以便向计量系统提供数据，并且其中传感器包括至少一个光学元件以在抛光期间检测分层。该方法包括抛光最上面的薄膜层的至少一部分，并且在最上层被抛光时检查最上面的薄膜层下面的层的至少一部分用于分层。

90. 发明授权

US06684172B1 Sensor to predict void free films using various grating structures and characterize fill performance 失效
标题翻译：传感器预测使用各种光栅结构的无空隙膜，并表征填充性能
公开(公告)号：US06684172B1
公开(公告)日：2004-01-27
申请号：US10034165
申请日：2001-12-27
申请人： Ramkumar Subramanian , Steven C. Avanzino , Christopher F. Lyons , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Cyrus E. Tabery
发明人： Ramkumar Subramanian , Steven C. Avanzino , Christopher F. Lyons , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Cyrus E. Tabery
IPC分类号： G01L2500
CPC分类号： C23C16/52 , C23C14/547 , C23C18/1675 , C25D21/12 , H01L21/76877
摘要： One aspect of the invention relates to a metal fill process and systems therefor involving providing a standard calibration wafer having a plurality of fill features of known dimensions in a metalization tool; depositing a metal material over the standard calibration wafer; monitoring the deposition of metal material using a sensor system, the sensor system operable to measure one or more fill process parameters and to generate fill process data; controlling the deposition of metal material to minimize void formation using a control system wherein the control system receives fill process data from the sensor system and analyzes the fill process data to generate a feed-forward control data operative to control the metalization tool; and depositing metal material over a production wafer in the metalization tool using the fill process data generated by the sensor system and the control system. The invention further relates to tool characterization processes and systems therefor.
摘要翻译：本发明的一个方面涉及一种金属填充方法及其系统，其涉及在金属化工具中提供具有已知尺寸的多个填充特征的标准校准晶片; 在标准校准晶片上沉积金属材料; 使用传感器系统监测金属材料的沉积，所述传感器系统可操作以测量一个或多个填充过程参数并产生填充过程数据; 控制金属材料的沉积以最小化使用控制系统的空隙形成，其中控制系统从传感器系统接收填充过程数据并分析填充过程数据以产生可操作以控制金属化工具的前馈控制数据; 以及使用由传感器系统和控制系统产生的填充过程数据在金属化工具中的生产晶片上沉积金属材料。本发明还涉及其工具表征过程及其系统。

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