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1. 发明授权

US06982043B1 Scatterometry with grating to observe resist removal rate during etch 有权
标题翻译：用光栅进行散射测量以观察蚀刻期间的抗蚀剂去除率
公开(公告)号：US06982043B1
公开(公告)日：2006-01-03
申请号：US10382181
申请日：2003-03-05
申请人： Ramkumar Subramanian , Bharath Rangarajan , Catherine B. Labelle , Bhanwar Singh , Christopher F. Lyons
发明人： Ramkumar Subramanian , Bharath Rangarajan , Catherine B. Labelle , Bhanwar Singh , Christopher F. Lyons
IPC分类号： B44C1/22
CPC分类号： H01L22/12 , H01L22/26
摘要： Disclosed are a system and method for monitoring a patterned photoresist clad-wafer structure undergoing an etch process. The system includes a semiconductor wafer structure comprising a substrate, one or more intermediate layers overlying the substrate, and a first patterned photoresist layer overlying the intermediate layers, the semiconductor wafer structure being etched through one or more openings in the photoresist layer; a wafer-etch photoresist monitoring system programmed to obtain data relating to the photoresist layer as the etch process progresses; a pattern-specific grating aligned with the wafer structure and employed in conjunction with the monitoring system, the grating having at least one of a pitch and a critical dimension identical to the first patterned photoresist layer; and a wafer processing controller operatively connected to the monitoring system and adapted to receive data from the monitoring system in order to determine adjustments to a subsequent wafer clean process.
摘要翻译：公开了用于监测经历蚀刻工艺的图案化光致抗蚀剂包覆晶片结构的系统和方法。该系统包括半导体晶片结构，其包括衬底，覆盖衬底的一个或多个中间层和覆盖中间层的第一图案化光致抗蚀剂层，半导体晶片结构通过光致抗蚀剂层中的一个或多个开口进行蚀刻; 晶片蚀刻光刻胶监测系统被编程为随着蚀刻工艺的进行获得与光致抗蚀剂层有关的数据; 与晶片结构对准并与监视系统结合使用的图案特定光栅，光栅具有与第一图案化光致抗蚀剂层相同的间距和临界尺寸中的至少一个; 以及晶片处理控制器，可操作地连接到所述监控系统并且适于从所述监控系统接收数据，以便确定随后的晶片清洁过程的调整。

2. 发明授权

US06771356B1 Scatterometry of grating structures to monitor wafer stress 失效
标题翻译：光栅结构的散射法监测晶片应力
公开(公告)号：US06771356B1
公开(公告)日：2004-08-03
申请号：US10050626
申请日：2002-01-16
申请人： Christopher F. Lyons , Bhanwar Singh , Steven C. Avanzino , Khoi A. Phan , Bharath Rangarajan , Ramkumar Subramanian , Cyrus E. Tabery
发明人： Christopher F. Lyons , Bhanwar Singh , Steven C. Avanzino , Khoi A. Phan , Bharath Rangarajan , Ramkumar Subramanian , Cyrus E. Tabery
IPC分类号： G01B1116
CPC分类号： G01B11/165
摘要： A system for monitoring a fabrication process is provided. The system includes one or more light sources, each light source directing light to one or more gratings on a wafer. Light reflected from the gratings is collected by a measuring system that processes the collected light. The collected light is indicative of distortion due to stress at respective portions of the wafer. The measuring system provides distortion/stress related data to a processor that determines the acceptability of the distortion of the respective portions of the wafer. The collected light may be analyzed by scatterometry systems to produce scatterometry signatures associated with distortion and to produce feed-forward control information that can be employed to control semiconductor fabrication processes.
摘要翻译：提供了一种用于监视制造工艺的系统。该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个光栅。从光栅反射的光被处理收集的光的测量系统收集。所收集的光指示由于晶片的各个部分处的应力引起的变形。测量系统向处理器提供失真/应力相关数据，该处理器确定晶片各部分的失真的可接受性。收集的光可以通过散射测量系统进行分析，以产生与失真相关联的散射仪签名并产生可用于控制半导体制造过程的前馈控制信息。

3. 发明授权

US06187666B1 CVD plasma process to fill contact hole in damascene process 有权
标题翻译： CVD等离子体工艺在镶嵌工艺中填充接触孔
公开(公告)号：US06187666B1
公开(公告)日：2001-02-13
申请号：US09328148
申请日：1999-06-08
申请人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
发明人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/312 , H01L21/76831 , H01L2221/1063
摘要： The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.
摘要翻译：本发明涉及在绝缘材料层中制造互连线和通孔的方法。在绝缘材料层中形成通孔。形成保护材料以至少与通孔的边缘和侧壁共形，所述保护材料有助于屏蔽通孔的至少边缘和侧壁至沟槽蚀刻步骤。执行沟槽蚀刻步骤以在绝缘材料中形成沟槽开口。通孔和沟槽填充有导电金属。

4. 发明授权

US06790790B1 High modulus filler for low k materials 失效
标题翻译：用于低k材料的高模量填料
公开(公告)号：US06790790B1
公开(公告)日：2004-09-14
申请号：US10302227
申请日：2002-11-22
申请人： Christopher F. Lyons , Bharath Rangarajan
发明人： Christopher F. Lyons , Bharath Rangarajan
IPC分类号： H01L2131
CPC分类号： H01L21/31058 , H01L21/02118 , H01L21/0212
摘要： Disclosed are methods for processing a low k material involving providing a low k material layer comprising one or more low k polymer materials and one or more high modulus fillers on a semiconductor substrate, and chemical mechanical polishing the low k material layer so as to remove a portion of the low k material layer from the semiconductor substrate without substantially damaging unremoved portions of the low k material layer. In this connection, low k material layers for a semiconductor structure containing one or more low k polymer materials and one or more high modulus fillers are disclosed, as well as methods of making the low k material layers.
摘要翻译：公开了一种处理低k材料的方法，包括在半导体衬底上提供包含一种或多种低k聚合物材料和一种或多种高模量填料的低k材料层，以及化学机械抛光低k材料层，以除去来自半导体衬底的低k材料层的一部分，而不会基本上损坏低k材料层的未被除去的部分。在这方面，公开了用于包含一种或多种低k聚合物材料和一种或多种高模量填料的半导体结构的低k材料层，以及制备低k材料层的方法。

5. 发明授权

US06684172B1 Sensor to predict void free films using various grating structures and characterize fill performance 失效
标题翻译：传感器预测使用各种光栅结构的无空隙膜，并表征填充性能
公开(公告)号：US06684172B1
公开(公告)日：2004-01-27
申请号：US10034165
申请日：2001-12-27
申请人： Ramkumar Subramanian , Steven C. Avanzino , Christopher F. Lyons , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Cyrus E. Tabery
发明人： Ramkumar Subramanian , Steven C. Avanzino , Christopher F. Lyons , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Cyrus E. Tabery
IPC分类号： G01L2500
CPC分类号： C23C16/52 , C23C14/547 , C23C18/1675 , C25D21/12 , H01L21/76877
摘要： One aspect of the invention relates to a metal fill process and systems therefor involving providing a standard calibration wafer having a plurality of fill features of known dimensions in a metalization tool; depositing a metal material over the standard calibration wafer; monitoring the deposition of metal material using a sensor system, the sensor system operable to measure one or more fill process parameters and to generate fill process data; controlling the deposition of metal material to minimize void formation using a control system wherein the control system receives fill process data from the sensor system and analyzes the fill process data to generate a feed-forward control data operative to control the metalization tool; and depositing metal material over a production wafer in the metalization tool using the fill process data generated by the sensor system and the control system. The invention further relates to tool characterization processes and systems therefor.
摘要翻译：本发明的一个方面涉及一种金属填充方法及其系统，其涉及在金属化工具中提供具有已知尺寸的多个填充特征的标准校准晶片; 在标准校准晶片上沉积金属材料; 使用传感器系统监测金属材料的沉积，所述传感器系统可操作以测量一个或多个填充过程参数并产生填充过程数据; 控制金属材料的沉积以最小化使用控制系统的空隙形成，其中控制系统从传感器系统接收填充过程数据并分析填充过程数据以产生可操作以控制金属化工具的前馈控制数据; 以及使用由传感器系统和控制系统产生的填充过程数据在金属化工具中的生产晶片上沉积金属材料。本发明还涉及其工具表征过程及其系统。

6. 发明授权

US06245493B1 Method for reducing surface reflectivity by increasing surface roughness 有权
标题翻译：通过增加表面粗糙度来降低表面反射率的方法
公开(公告)号：US06245493B1
公开(公告)日：2001-06-12
申请号：US09205738
申请日：1998-12-04
申请人： Bhanwar Singh , Bharath Rangarajan , Sanjay K. Yedur , Michael K. Templeton , Christopher F. Lyons
发明人： Bhanwar Singh , Bharath Rangarajan , Sanjay K. Yedur , Michael K. Templeton , Christopher F. Lyons
IPC分类号： G03F700
CPC分类号： H01L21/0276 , G03F7/091 , G03F7/16 , H01L21/3105
摘要： A method for creating a roughened surface on a material exposed to light during a photolithographic process is provided. The roughened surface is created on a surface of the material via a plasma etch process. The roughened surface diffuses light incident to the material such that the diffused light causes insubstantial damage to a photoresist subsequently formed on the material.
摘要翻译：提供了一种在光刻过程中在暴露于光的材料上产生粗糙表面的方法。通过等离子体蚀刻工艺在材料的表面上形成粗糙表面。粗糙表面扩散入射到材料的光，使得漫射的光对随后在材料上形成的光致抗蚀剂造成非实质的损坏。

7. 发明授权

US06864024B1 Real-time control of chemically-amplified resist processing on wafer 失效
标题翻译：化学放大抗蚀剂加工在晶圆上的实时控制
公开(公告)号：US06864024B1
公开(公告)日：2005-03-08
申请号：US10302225
申请日：2002-11-22
申请人： Christopher F. Lyons , Bharath Rangarajan
发明人： Christopher F. Lyons , Bharath Rangarajan
IPC分类号： A61N5/00 , G03C5/00 , G03F7/038 , G03F7/039 , G03F9/00
CPC分类号： G03F7/0382 , G03F7/0392
摘要： One aspect of the present invention relates to a system and method for controlling environmental acid scavengers in real time during pattern exposure of a chemically amplified resist-clad wafer. The system includes a semiconductor wafer comprising a chemically amplified resist layer formed over a substrate layer, wherein a first portion of the resist layer has been removed to expose an area of the substrate layer in order to form a probe area; an exposure system programmed to implement an exposure process to transfer a device pattern onto at least a second portion of the resist layer; and a monitoring system adapted to detect chemical signals about the probe area in order to control the integrity of the resist layer during the exposure process. The method involves feeding data back to the on-going exposure process in order to effect an immediate change in the process.
摘要翻译：本发明的一个方面涉及在化学放大的抗蚀剂包覆晶片的图案曝光期间实时控制环境酸清除剂的系统和方法。该系统包括半导体晶片，其包括在衬底层上形成的化学放大抗蚀剂层，其中已除去抗蚀剂层的第一部分以暴露衬底层的区域以形成探针区域; 曝光系统被编程为实现曝光过程以将装置图案转印到抗蚀剂层的至少第二部分上; 以及适于检测关于探针区域的化学信号以便在曝光过程期间控制抗蚀剂层的完整性的监测系统。该方法涉及将数据馈送回正在进行的曝光过程，以便立即改变过程。

8. 发明授权

US06654660B1 Controlling thermal expansion of mask substrates by scatterometry 有权
标题翻译：通过散射法控制掩模基板的热膨胀
公开(公告)号：US06654660B1
公开(公告)日：2003-11-25
申请号：US10287292
申请日：2002-11-04
申请人： Bhanwar Singh , Christopher F. Lyons , Bharath Rangarajan , Khoi A. Phan , Ramkumar Subramanian
发明人： Bhanwar Singh , Christopher F. Lyons , Bharath Rangarajan , Khoi A. Phan , Ramkumar Subramanian
IPC分类号： G06F1900
CPC分类号： G03F7/70425 , G03F7/70875
摘要： One aspect of the present invention relates to a system and method for controlling thermal expansion on an EUV mask during EUV photolithography. The system includes an EUV photolithography system for irradiating one or more layers of a wafer through one or more gratings of a patterned EUV mask, whereby heat accumulates on at least a portion of the patterned EUV mask during the irradiation of the one or more layers of the wafer; an EUV mask inspection system for monitoring the one or more gratings on the mask to detect expansion therein, the inspection system producing data relating to the mask; and a temperature control system operatively coupled to the inspection system for making adjustments to the EUV photolithography system in order to compensate for the detected expansion on the mask. The method involves employing feedback and feed forward control to optimize the current and future EUV photolithography processes.
摘要翻译：本发明的一个方面涉及一种用于在EUV光刻期间控制EUV掩模上的热膨胀的系统和方法。该系统包括用于通过图案化的EUV掩模的一个或多个光栅照射晶片的一个或多个层的EUV光刻系统，由此在图案化的EUV掩模的照射期间在图案化的EUV掩模的至少一部分上积聚热量晶圆; 用于监视所述掩模上的所述一个或多个光栅以检测其中的扩展的EUV掩模检查系统，所述检查系统产生与所述掩模有关的数据; 以及温度控制系统，其可操作地耦合到所述检查系统，以对EUV光刻系统进行调整，以便补偿所述掩模上检测到的膨胀。该方法涉及采用反馈和前馈控制来优化当前和未来的EUV光刻工艺。

9. 发明授权

US06808591B1 Model based metal overetch control 有权
标题翻译：基于型号的金属防腐控制
公开(公告)号：US06808591B1
公开(公告)日：2004-10-26
申请号：US10021531
申请日：2001-12-12
申请人： Khoi A. Phan , Bharath Rangarajan , Christopher F. Lyons , Steven C. Avanzino , Ramkumar Subramanian , Bhanwar Singh , Cyrus E. Tabery
发明人： Khoi A. Phan , Bharath Rangarajan , Christopher F. Lyons , Steven C. Avanzino , Ramkumar Subramanian , Bhanwar Singh , Cyrus E. Tabery
IPC分类号： H01L21302
CPC分类号： H01L21/67253 , H01L21/32136
摘要： A systems and methodologies are provided for metal overetch control. Metal overetch processes are controlled by utilizing overetch device models to determine overetch times or overetch endpoints. The systems and methodologies reduce the need for manual testing and manual overetch characterization. An overetch system includes a metal etcher, a target device and an overetch controller. The target device is located in or on the metal etcher. The overetch controller is coupled to the metal etcher. The overetch controller controls overetching of the target device by the metal etcher. The overetch controller includes an overetch time controller, a set of etch control models and a control system.
摘要翻译：提供了用于金属过程控制的系统和方法。通过利用过滤设备模型来确定金属过蚀刻过程以确定过蚀刻时间或过程延伸端点。系统和方法减少了手动测试和手动过程表征的需要。一种过蚀系统包括金属蚀刻机，目标装置和过程控制器。目标设备位于金属蚀刻机中或其上。该过程控制器耦合到金属蚀刻器。过程控制器通过金属蚀刻器控制目标器件的过蚀刻。该过程控制器包括一个过时延时间控制器，一组蚀刻控制模型和一个控制系统。

10. 发明授权

US06605855B1 CVD plasma process to fill contact hole in damascene process 有权
标题翻译： CVD等离子体工艺在镶嵌工艺中填充接触孔
公开(公告)号：US06605855B1
公开(公告)日：2003-08-12
申请号：US09650538
申请日：2000-08-30
申请人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
发明人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
IPC分类号： H01L2900
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/312 , H01L21/76831 , H01L2221/1063
摘要： The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.
摘要翻译：本发明涉及在绝缘材料层中制造互连线和通孔的方法。在绝缘材料层中形成通孔。形成保护材料以至少与通孔的边缘和侧壁共形，所述保护材料有助于屏蔽通孔的至少边缘和侧壁至沟槽蚀刻步骤。执行沟槽蚀刻步骤以在绝缘材料中形成沟槽开口。通孔和沟槽填充有导电金属。

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